{"id":1033,"date":"2025-10-31T06:00:00","date_gmt":"2025-10-31T06:00:00","guid":{"rendered":"http:\/\/localhost:8080\/sk-hynix-showcases-full-stack-ai-memory-portfolio-at-2025-ocp-global-summit\/"},"modified":"2026-06-11T12:59:56","modified_gmt":"2026-06-11T12:59:56","slug":"sk-hynix-showcases-full-stack-ai-memory-portfolio-at-2025-ocp-global-summit","status":"publish","type":"post","link":"https:\/\/news.skhynix.com\/en\/sk-hynix-showcases-full-stack-ai-memory-portfolio-at-2025-ocp-global-summit\/","title":{"rendered":"SK hynix Showcases Full-Stack AI Memory Portfolio at 2025 OCP Global Summit"},"content":{"rendered":"
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SK hynix showcased its full-stack AI memory portfolio for enhancing AI and data center infrastructure at the 2025 OCP Global Summit<\/a> in San Jose, California from October 13\u201316.<\/p>\n

The OCP Global Summit is a conference hosted by the Open Compute Project (OCP), the world\u2019s largest open data center technology collaboration community. Held under the theme \u201cLeading the Future of AI\u201d, this year\u2019s event welcomed experts from leading global companies and developers to share the latest trends in data center and AI infrastructure and discuss developing industry solutions.\u00a0<\/span><\/p>\n

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\u25b2 Visitors gather at SK hynix\u2019s booth<\/p>\n

Under the slogan \u201cMEMORY, Powering AI and Tomorrow,\u201d SK hynix presented a range of innovative technologies which improve the performance and efficiency of AI infrastructure. The company\u2019s interactive booth was organized into four sections \u2014 HBM* <\/sup>, AiM* <\/sup>, DRAM, and eSSDs* <\/sup> \u2014 and featured product-based character designs, 3D models of key technologies, and live demonstrations.<\/p>\n

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* <\/sup>High Bandwidth Memory (HBM): A high-value, high-performance memory product which vertically interconnects multiple DRAM chips and dramatically increases data processing speed in comparison to conventional DRAM products. There are six generations of HBM, starting with the original HBM followed by HBM2, HBM2E, HBM3, HBM3E, and HBM4.
\n* <\/sup>Accelerator-in-Memory (AiM): A next-generation solution that integrates computational capabilities into memory.
\n* <\/sup>Enterprise Solid State Drive (eSSD): An enterprise-grade SSD used in servers and data centers.<\/p>\n

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The centerpiece of SK hynix\u2019s booth was its groundbreaking 12-layer HBM4. In September 2025, the company became the first in the world to complete development of HBM4 and establish the product\u2019s mass production system<\/a>. Featuring 2,048 input\/output (I\/O) channels, twice that of the previous generation, HBM4 offers increased bandwidth and over 40% greater power efficiency. These specifications make it optimized for ultra-high-performance AI computing systems.<\/p>\n

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\u25b2 SK hynix\u2019s HBM4 and HBM3E on display alongside NVIDIA\u2019s GB300 Grace Blackwell GPU<\/p><\/div><\/a>

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\u25b2 The 12-layer HBM4 and 12-layer HBM3E<\/p><\/div><\/a>

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\u25b2 NVIDIA\u2019s next-generation GB300 GPU module equipped with SK hynix\u2019s HBM3E<\/p><\/div><\/a>

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\u25b2 A 3D model of technologies applied to HBM4<\/p><\/div><\/a>

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The company also displayed its 36 GB HBM3E, the industry\u2019s highest capacity HBM available on the market, applied to NVIDIA\u2019s next-generation GB300 Grace\u2122 Blackwell GPU. Next to the display, there was a 3D model that helped visitors better the advanced packaging technologies used in HBM such as TSV4 <\/sup>and Advanced MR-MUF* <\/sup>.<\/p>\n

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* <\/sup>Through silicon-via (TSV): A technology that connects vertically stacked DRAM chips by drilling thousands of microscopic holes through the silicon and linking the layers with vertical electrodes.
\n* <\/sup>Advanced Mass Reflow-Molded Underfill (MR-MUF): A next-generation MR-MUF technology which offers enhanced warpage control, enabling stacking of chips 40% thinner than previous generations. With new protective materials, it also provides improved heat dissipation.<\/p>\n

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\u25b2 An AiMX card on display at the booth<\/p>\n<\/figure>\n

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In the AiM section, SK hynix ran a live demonstration of its AiMX* <\/sup> card which includes multiple GDDR6-AiM chips. The demonstration featured a server equipped with four AiMX cards and two NVIDIA H100 GPUs, highlighting how AiMX is optimized for attention* <\/sup> operations \u2014 the core computation in LLMs* <\/sup> \u2014 by enhancing the speed and efficiency of memory-bound* <\/sup> workloads. AiMX also improves KV-cache* <\/sup> utilization during long question-and-answer sequences, mitigating the memory wall* <\/sup> issue. During the demonstration, Meta\u2019s Llama 3 LLM was run on a vLLM* <\/sup>, showing that multiple users can simultaneously and seamlessly access a chatbot service. Through this, visitors could witness first-hand the technical excellence of SK hynix\u2019s AiM products.<\/p>\n

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* <\/sup>AiM-based Accelerator (AiMX): SK hynix\u2019s accelerator card featuring a GDDR6-AiM chip which is specialized for large language models (LLMs) \u2014 AI systems such as ChatGPT trained on massive text datasets.
\n* <\/sup>Attention: An algorithmic technique that dynamically determines which parts of input data to focus on.
\n* <\/sup>Large language model (LLM): An AI model trained on massive datasets that understands and generates natural language processing tasks.
\n* <\/sup>Memory-bound: A situation in which system performance is limited not by the processor\u2019s computational power but by memory access speed, causing delays while waiting for data access.
\n* <\/sup>Key-Value (KV) cache: A technology that stores and reuses previously computed Key and Value vectors, preserving context from earlier inputs to reduce redundant calculations and respond more efficiently.
\n* <\/sup>Memory wall: A bottleneck that occurs when memory access speed lags behind data processor speed.
\n* <\/sup>Virtual large language model (vLLM): An AI framework designed for efficient and optimized LLM inference.<\/p>\n

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\u25b2 CXL-based solutions enable flexible expansion of system memory capacity and bandwidth<\/p>\n

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SK hynix\u2019s booth also featured various CXL* <\/sup>-based solutions that allow flexible expansion of system memory capacity and bandwidth. These included a distributed LLM inference system that connects multiple servers and GPUs without a network using CXL pooled memory, which allows multiple processors, or hosts, to flexibly share memory. The company also showcased the performance of its CXL Memory Module\u2013Accelerator (CMM-Ax), which adds computing capability to CXL memory, by applying it to SK Telecom\u2019s Petasus AI Cloud.<\/p>\n

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* <\/sup>Compute Express Link (CXL):\u00a0A next-generation solution designed to integrate CPU, GPU, memory and other key computing system components \u2014 enabling unparalleled efficiency for large-scale and ultra-high-speed computations.<\/p>\n

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In addition, SK hynix verified the performance benefits of a tiering solution which helps utilize various types of memory in an optimal configuration. The solution was enabled by CHMU* <\/sup>, which was first introduced in the CXL 3.2 standard. A separate demonstration drew significant attention for highlighting the enhanced prompt caching* <\/sup> capabilities of LLM service systems based on CMM-DDR5, resulting in shorter response times to user requests.<\/p>\n

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* <\/sup>CXL Hot-range Monitoring Unit (CHMU): A technology that monitors the usage frequency of multiple memory devices to support efficient system operation and device optimization.
\n* <\/sup>Prompt caching: A technology that stores previously processed prompts in AI models to shorten processing time and reduce costs during repeated use.<\/p>\n

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\u25b2 A diverse range of DRAM solutions showcased at the booth<\/p>\n<\/figure>\n

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In the DRAM section, SK hynix presented its DDR5-based module lineup targeting the next-generation server market. In particular, the display drew attention for featuring a diverse product portfolio with a range of capacities and form factors. These included RDIMM* <\/sup> and MRDIMM17 <\/sup>products which leverage the 1c18 <\/sup>node, the sixth generation of the 10 nm process technology, as well as 3DS* <\/sup> DDR5 RDIMM and DDR5 Tall MRDIMM.<\/p>\n

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* <\/sup>Registered Dual In-line Memory Module (RDIMM): A server memory module product in which multiple DRAM chips are mounted on a substrate.
\n* <\/sup>Multiplexed Rank Dual In-line Memory Module (MRDIMM): A server memory module product with enhanced speed by simultaneously operating two ranks \u2014 the basic operating units of the module.
\n* <\/sup>1c: The 10 nm DRAM process technology has progressed through six generations: 1x, 1y, 1z, 1a, 1b, and 1c.
\n* <\/sup>3D Stacked Memory (3DS): A high-performance memory solution in which two or more DRAM chips are packaged together and interconnected using TSV technology.<\/p>\n

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\u25b2 Various eSSD products displayed in the eSSD section<\/p>\n

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The eSSD section featured various storage solutions optimized for servers and data centers. These included the PS1010 E3.S and U.2 models based on 176-layer 4D NAND and PEB110 E1.S built on 238-layer 4D NAND. In addition, the company showcased its 245 TB PS1101 E3.L \u2014 an ultra-high-capacity model built on the industry\u2019s highest 321-layer QLC* <\/sup>. The eSSD lineup is designed to meet diverse server environments and performance requirements, ranging from high-performance PCIe Gen 5 NVMe* <\/sup> to SATA* <\/sup> interfaces for compact servers.<\/p>\n

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* <\/sup>Quad-level cell (QLC): A type of memory cell used in NAND flash that stores four bits of data in a single cell. NAND flash is categorized as single-level cell (SLC), multi-level cell (MLC), triple-level cell (TLC), QLC, and penta-level cell (PLC) depending on how many data bits can be stored in one cell.
\n* <\/sup>Non-Volatile Memory express (NVMe): A data transfer protocol that maximizes SSD performance by utilizing PCIe, a high-speed serial communication interface.
\n* <\/sup>Serial ATA(SATA): A traditional interface widely used in hard drives and SSDs. Although it offers lower speeds compared to NVMe, it provides high compatibility and stability, making it suitable for small-scale servers and entry-level PCs.<\/p>\n

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\u25b2 SK hynix shared its industry expertise through presentation sessions<\/p><\/div><\/a>

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\u25b2 SK hynix shared its industry expertise through presentation sessions<\/p><\/div><\/a>

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\u25b2 Vice President Chunsung Kim, head of eSSD Product Development, presenting on storage solutions for the AI era<\/p><\/div><\/a>

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\u25b2 \u201cThomas\u201d Wonha Choi of Next-Gen Memory & Storage speaking on how storage can meet market demands<\/p><\/div><\/a>

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As well as displaying its groundbreaking products, SK hynix shared its next-generation storage strategy in presentation sessions. Vice President Chunsung Kim, head of eSSD Product Development, gave a presentation titled \u201cBeyond SSD: SK hynix AIN Family Redefining Storage as the Core Enabler of AI at Scale.\u201d During the talk, Kim introduced high-capacity, high-performance solutions for the AI era and outlined strategies to strengthen product competitiveness. Meanwhile, \u201cThomas\u201d Wonha Choi of Next-Gen Memory & Storage presented a talk titled \u201cConceptualizing Next Generation Memory & Storage Optimized for AI Inference.\u201d His session proposed directions to meet performance and power needs in line with new market conditions and customer demand. At the OCP Global Summit 2025, SK hynix took another step forward in reinforcing global collaboration and advancing its technological strategy. Building on this momentum, the company will continue to deliver innovative solutions for the rapidly evolving AI infrastructure landscape as it evolves into a full-stack AI memory provider.<\/p>\n

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