{"id":11352,"date":"2026-07-22T05:00:49","date_gmt":"2026-07-22T05:00:49","guid":{"rendered":"https:\/\/news.skhynix.com\/en\/?p=11352"},"modified":"2026-07-22T05:25:43","modified_gmt":"2026-07-22T05:25:43","slug":"research-inside-ep1","status":"publish","type":"post","link":"https:\/\/news.skhynix.com\/en\/research-inside-ep1\/","title":{"rendered":"[Inside the Research] SK hynix\u2019s CTI innovation advances 176-layer 3D NAND toward mass production"},"content":{"rendered":"
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As a full-stack AI memory creator, SK hynix offers a portfolio of AI memory solutions optimized for AI systems \u2014 including High Bandwidth Memory (HBM), AI-DRAM, and AI-NAND flash \u2014 built on foundational innovation from SK hynix engineers and researchers.To highlight the research that underpins these solutions as well as the company\u2019s broader technology roadmap, the SK hynix Newsroom is launching an article series titled [Inside the Research]. The first installment examines CTI, a technology designed to push past the limits of scaling in ultra-high-stack 3D NAND of 176 layers and beyond.
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\n[Read the Paper]<\/strong>
\n\u2219 Title:<\/strong> A Highly Scalable Isolated Charge Trap Nitride Layer Implemented in a 176-layer 3D NAND Flash with Superior Threshold Voltage Distribution and Charge Retention
\n\u2219 Published in:<\/strong> 2025 IEEE International Electron Devices Meeting (IEDM)
\n<\/strong>\u2219 Author:<\/strong> Sangwan Jin, Technical Leader, Materials Development, SK hynix
\n<\/strong><\/strong><\/strong>(Summary<\/a>) | (Full Text<\/a>)<\/p>\n<\/div>\n

Traditionally, 3D NAND flash (hereafter referred to as \u201cNAND\u201d) capacity was increased by stacking more cells*<\/span> vertically, but as stack height continued to increase, so did cost and process complexity. The industry therefore began shifting toward increasing capacity by reducing cell size and fitting more cells within the same overall height. In other words, the total stack height is maintained while the tier pitch is reduced and the number of layers increases. As cells become smaller, however, the spacing between vertically adjacent cells also narrows, making electrical interference more severe. SK hynix\u2019s response to this new challenge is charge trap nitride isolation (CTI).<\/p>\n

* <\/span>Cell: The smallest unit of data storage in a semiconductor device.<\/div>\n
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Research background: Understanding NAND\u2019s scaling limits<\/h3>\n
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First, a review of the fundamentals: NAND cells are typically stacked vertically using different manufacturing methods, and SK hynix employs a CTN-based structure*<\/span>.<\/p>\n

* <\/span>Charge trap nitride (CTN): A technology that stores electrons, or data, in an insulating nitride layer. Compared with floating-gate technology, which stores charge in a conductor, CTN can reduce cell area while improving read and write performance.<\/div>\n

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\u25b2 [Figure 1] The NAND Flash Cell-formation Process<\/p>\n

How is a NAND cell made?
\n<\/strong>As shown in Figure 1, thin films of silicon nitride and silicon oxide are stacked repeatedly on a wafer, similar to precisely layering sheets of paper only tens of nanometers thick. Next, a deep vertical channel hole is etched through the stack. The inner wall of the hole is then coated with a blocking oxide, CTN for storing electrons*<\/span>, a tunnel oxide, and polysilicon. This process forms the memory cell. 3D NAND is built by vertically stacking these cells, with layer counts scaling from 100 to 200, 300 and beyond.<\/p>\n

* <\/span>Electron: A negatively charged particle. In NAND, cells distinguish between 0 and 1 depending on the number of stored electrons.<\/div>\n

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\u25b2 [Figure 2] The Conventional CTI Implementation Process<\/p>\n

What happens when cells are scaled down?
\n<\/strong>Reducing cell size and narrowing the distance between vertically adjacent cells enables higher density and greater capacity but also increases cell-to-cell interference. This occurs when the electric field generated by electrons stored in one cell affects neighboring cells, leading to threshold-voltage (Vth<\/sub>) shifts and errors caused by electron migration.<\/p>\n

Threshold voltage (Vth<\/sub>) is the minimum voltage required to allow current to flow through a cell. The more electrons stored in the cell, the higher the Vth<\/sub>; the fewer electrons stored, the lower the Vth<\/sub>. When reading data, NAND determines which data state is stored by identifying the Vth<\/sub> level. If Vth<\/sub> shifts, data read errors can occur. As cell spacing narrows, cell-to-cell interference becomes more severe, and stored electrons may leak into neighboring cells, potentially corrupting the stored data.<\/p>\n

CTI was developed to address this limitation. As shown in Figure 2, conventional CTI isolates the CTN that stores electrons by etching the silicon nitride layer and using silicon oxide as an isolation barrier. In conventional structures, the CTN is formed as a continuous layer. CTI physically separates the upper and lower CTN regions with an isolation structure. As a result, CTI can maintain operational reliability and improve charge retention even when the cell pitch is reduced. These advantages have kept CTI under active discussion for more than a decade.<\/p>\n

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Research breakthrough: Overcoming NAND scaling limits with 176-layer CTI<\/h3>\n
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Although CTI was studied for years, it wasn\u2019t adopted for mass production because of its technical limitations. In conventional CTI, pockets are created by etching the silicon nitride layer before the CTN material is deposited into them. However, this etching process caused the channel holes to widen.<\/p>\n

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\u25b2 [Figure 3] Differences in Channel-Hole Count due to Channel-Hole Diameter<\/p>\n

Because each vertically etched channel hole in NAND contains hundreds of memory cells, any increase in channel-hole diameter reduces the number of channel holes that can fit within the same area, resulting in lower integration density. Another challenge was controlling etch uniformity across the wafer, since variations in etch depth led to inconsistent pocket sizes. As a result, conventional CTI was difficult to implement in commercial products and remained mostly limited to demonstrating the technology\u2019s effectiveness in research settings.<\/p>\n

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\u25b2 [Figure 4] The New CTI Implementation Process<\/p>\n

What makes SK hynix\u2019s new CTI technology different?
\n<\/strong>SK hynix\u2019s new CTI technology forms the pocket by depositing an oxide barrier and then filling that space with CTN material. Because this method does not etch the silicon nitride layer, it does not enlarge the channel hole. This makes it possible to implement the CTI structure without compromising NAND integration density. The deposition process also has an advantage over etching in securing uniformity between the upper and lower regions of the channel hole. In this research, SK hynix achieved a uniform characteristic distribution across the full 176-layer stack, addressing the process non-uniformity of conventional CTI and demonstrating manufacturability.<\/p>\n

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\u25b2 [Figure 5] A Comparison of Conventional CTI with SK hynix\u2019s New CTI Process<\/p>\n

What are the advantages of the new CTI technology?
\n<\/strong>The key achievement of this research is that it makes commercial deployment of CTI a practical reality. Previous CTI research was largely limited to test vehicles of around 10 layers, but SK hynix has now successfully implemented a CTI structure in a production-scale 176-layer NAND device for the first time in the industry. Compared to conventional structure, this innovation reduces cell-to-cell interference by more than 30% and improves charge retention by more than 45%<\/p>\n

As a result, the Vth<\/sub> distribution has become more uniform, improving data-read reliability, while reduced electron migration has significantly strengthened long-term durability. This also enabled the company to shrink the size of individual memory cells by more than 10% \u2014 without concerns over Vth<\/sub> distortion or electron migration errors \u2014 thereby increasing NAND memory density. Due to these advantages, SK hynix sees this technology as a key enabler for overcoming the limits of vertical scaling in NAND.<\/p>\n

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Key concept: CTI explained<\/h3>\n
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\u25b2 CTI explained<\/p>\n

The CTN layer, which stores electrons, forms a continuous structure rather than being completely isolated from one memory cell to the next. Think of it as a long desk without partitions. Each memory cell is a designated seat, and the data is a book placed on that seat. Without partitions, books can easily spill into neighboring seats, making it difficult to tell whether a book belongs to one seat (0) or another (1). As the seats are packed more closely together, the books become more likely to get mixed up, and even a slight movement by a neighboring seat can cause interference.
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\nCTI solves this problem by clearly separating the seats. SK hynix developed a way to add dividers while preserving the overall structure of the original desk. This prevents books from mixing and minimizes interference from neighboring seats, even when the seats are placed more closely together.<\/p>\n<\/div>\n

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Mini interview: The present and future of CTI<\/h3>\n
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\u201cThis was particularly meaningful work because it opened up new possibilities for scaling technology that had seemed to be reaching a plateau,\u201d said Sangwan Jin, Technical Leader of Materials Development, reflecting on the research. The SK hynix Newsroom spoke with Jin about the latest developments in CTI technology and where the research is headed next.<\/p>\n

Q. What are the latest trends in CTI?
\n<\/strong>The effectiveness of CTI has already been sufficiently established across the industry, so the focus has now shifted to how it can be implemented in practice for high-layer stacks. Reducing process cost is another key challenge. In particular, many companies are investing in new deposition technologies and material development to maintain uniform cell size and shape while isolating the CTN layer.<\/p>\n

Q. What is the significance of SK hynix\u2019s new CTI technology?
\n<\/strong>While previous CTI research remained at the proof-of-concept stage, this project was a highly demanding effort to scale the technology to an actual production level. There were moments when unpredictable defects occurred repeatedly, forcing us to question whether implementation was even possible.<\/p>\n

However, our team of experts in device engineering, process technology, TCAD\/modeling*<\/span> and materials science formed a collaborative task force, repeating multidimensional analysis and simulation verification countless times until we overcame the technical limitations. I am confident that this project will pave the way for new possibilities for NAND R&D.<\/p>\n

* <\/span>Technology Computer-Aided Design (TCAD)\/Modeling: A simulation technique used to model and predict the structure and operation of semiconductor devices using computers.<\/div>\n

Q. What projects do you plan to pursue next?
\n<\/strong>I have since moved from device development to materials development, continuing to build on the experience of this project. My experience across process and device development made me keenly aware of the need for new materials, which motivated the move.<\/p>\n

I aim to leverage my understanding of materials to optimize both processes and devices. Ultimately, I hope to cultivate capabilities that span the broader semiconductor ecosystem, where process, device, and materials technologies are organically connected.<\/p>\n

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\n \n <\/div>\n<\/p><\/div>\n<\/div>\n","protected":false},"excerpt":{"rendered":"

As a full-stack AI memory creator, SK hynix offers a portfolio of AI memory solutions optimized for AI systems \u2014 including High Bandwidth Memory (HBM), AI-DRAM, and AI-NAND flash \u2014 built on foundational innovation from SK hynix engineers and researchers.To<\/p>\n","protected":false},"author":23,"featured_media":11363,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"_migrated_source_id":0,"footnotes":"","_members_access_role":[],"_members_access_error":""},"categories":[5],"tags":[1590,1592,1593,38,19,1591,669],"class_list":["post-11352","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-tech-and-ai","tag-176-layer-nand","tag-cti","tag-iedm","tag-ieee","tag-nand","tag-research-inside","tag-scaling"],"acf":[],"_links":{"self":[{"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/posts\/11352","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/users\/23"}],"replies":[{"embeddable":true,"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/comments?post=11352"}],"version-history":[{"count":18,"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/posts\/11352\/revisions"}],"predecessor-version":[{"id":11420,"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/posts\/11352\/revisions\/11420"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/media\/11363"}],"wp:attachment":[{"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/media?parent=11352"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/categories?post=11352"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/tags?post=11352"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}