{"id":12211,"date":"2026-08-07T14:00:04","date_gmt":"2026-08-07T05:00:04","guid":{"rendered":"https:\/\/news.skhynix.com\/en\/?p=12211"},"modified":"2026-08-07T14:00:04","modified_gmt":"2026-08-07T05:00:04","slug":"fms-2026","status":"publish","type":"post","link":"https:\/\/news.skhynix.com\/en\/fms-2026\/","title":{"rendered":"The Next-Generation Memory Architecture in the AI Era? SK hynix Charts the Direction at \u2018FMS 2026\u2019"},"content":{"rendered":"

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\u25b2 SK hynix exhibition booth overview at FMS 2026<\/p>\n

\u2018Future of Memory and Storage 2026 (FMS 2026)\u2019, the world\u2019s largest exhibition and conference in the memory and storage field, was held from August 4 to 6 (local time) at the Santa Clara Convention Center in California, USA. Once again this year, more than 350 AI experts gathered to exchange the latest technology trends and insights, while cutting-edge products and technical information set to shape the future of the AI industry were showcased on the exhibition floor. Over the three-day event, with attendees attentively inquiring about products and listening to technical explanations across every booth.<\/p>\n

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\u25b2 Visitors exploring the SK hynix exhibition booth<\/p><\/div><\/a>

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As AI technology becomes deeply woven into everyday life, demand for data centers has surged. This year\u2019s FMS reflected that shift, drawing strong interest in AI infrastructure across the board. Against this backdrop, SK hynix showcased a product portfolio spanning high-performance AI memory led by HBM*<\/span> and its latest NAND-based server memory, while demonstrating CXL*<\/span>-based memory expansion technology to prove its technical capabilities as a \u2018Full-Stack AI Memory Creator\u2019 poised to lead the AI era. In its keynote on the first day, the company also attracted significant attention by outlining strategic directions for next-generation AI memory solutions grounded in Tiered Memory*<\/span>.<\/p>\n

*<\/span> HBM (High Bandwidth Memory): A high-value, high-performance product that vertically connects multiple DRAM chips to increase capacity and dramatically improve data processing speed. HBM has been developed across generations: HBM \u2192 HBM2 \u2192 HBM2E \u2192 HBM3 \u2192 HBM3E \u2192 HBM4 \u2192 HBM4E.
\n*<\/span> CXL (Compute Express Link): An interface technology that efficiently connects memory, processors, and other components within a system to expand the limits of bandwidth and capacity.
\n*<\/span> Tiered Memory: An architecture that organizes memory of differing speed, capacity, and cost into tiers, then connects and optimizes them organically. As AI workloads grow more advanced, a single type of memory alone can no longer meet customer and market needs, making this approach increasingly important.<\/p>\n

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Presenting AI Infrastructure Optimization Strategies in the Agentic AI Era<\/h3>\n
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On the opening day, SK hynix Executive Vice President Kim Chun-sung (Head of Solution Development, and Vice President Kang Uk-song (Head of Next Generation Product Planning) took the stage as the third keynote speakers. Under the theme \u2018Orchestrating Efficient AI Infrastructure through Tiered Memory in the Era of Agentic AI,\u2019 the two speakers explored in depth how future memory architecture should evolve.<\/p>\n

They began by pointing out that as AI agents are rapidly commercialized, the volume of data AI must process is growing exponentially, demanding higher levels of processing speed and efficiency that single memory product alone cannot effectively address. As a solution, they proposed a next-generation architecture based on Tiered Memory, which organically connects and optimizes memory with different characteristics.<\/p>\n

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\u25b2 SK hynix Executive Vice President Kim Chun-sung, Head of Solution Development, delivering the keynote<\/p><\/div><\/a>

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\u25b2 SK hynix Vice President Kang Uk-song, Head of Next Generation Product Planning, delivering the keynote<\/p><\/div><\/a>

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\u201cAs AI expands from a focus on training to large-scale inference and, further, to Agentic AI, infrastructure competitiveness is no longer determined by the performance of individual memory products alone,\u201d said Kim Chun-sung, SK hynix Executive VP and Head of Solution Development. \u201cWhat determines overall efficiency is where each memory tier \u2014 HBM, DRAM, NAND (HBF), and SSD \u2014 is positioned and how it is connected to minimize data movement.\u201d He emphasized, \u201cGoing forward, the ability to implement an optimized architecture that encompasses all memory tiers will be the key to competitiveness in AI infrastructure.\u201d<\/p>\n

Vice President Kang added, \u201cSK hynix holds a broad portfolio that spans every tier of AI infrastructure, from HBM to CXL-based memory and eSSD.\u201d He stressed, \u201cGoing forward, SK hynix\u2019s role will be to work together with customers from the product design stage to identify and deliver the optimal solutions they need.\u201d<\/p>\n

In addition, throughout the three days of FMS 2026, SK hynix delivered a total of 12 Technical Session presentations, including two joint presentations, sharing its technical journey toward completing next-generation AI memory solutions and the key technical innovations identified along the way.<\/p>\n

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\u25b2 SK hynix Vice President Lim Eui-cheol (Head of Solution AT), during a panel discussion on HBF development with Google and Sandisk<\/p>\n

On the morning of the final day, Vice President Lim Eui-cheol, Head of Solution AT, took part in a panel discussion held under the theme \u2018Breaking the Memory Wall with High Bandwidth Flash.\u2019 Together with major industry players including Google and Sandisk, Lim led an in-depth discussion onHBF*<\/span>\u2019s development roadmap and technical possibilities.<\/p>\n

*<\/span> HBF (High Bandwidth Flash): A next-generation NAND solution with enhanced ultra-high-speed data transfer to efficiently process the rapidly growing volume of large-scale computational data. Like HBM, it maximizes performance by applying a logic process to the base die.<\/p>\n

Vice President Lim stated, \u201cHBF is a new concept in memory that applies TSV*<\/span> technology\u2014similar to HBM\u2014to achieve both the large capacity of traditional storage and high bandwidth comparable to DRAM. It holds significant potential to establish itself as a new memory tier between ultra-high-speed HBM and high-capacity SSDs.\u201d The Head of Soultion AT also highlighted HBF as a key solution for boosting AI system scalability and reducing operational costs, emphasizing the importance of a co-design approach that develops hardware and software together. Lim further explained that SK hynix is actively dedicating its efforts to securing next-generation technologies and establishing standardization in collaboration with major partners.<\/p>\n

*<\/span> TSV (Through Silicon Via): A packaging technology that connects chips vertically. Regarded as a core technology for implementing HBM, it dramatically reduces signal transmission distance and power consumption while greatly improving bandwidth.<\/p>\n

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From AI Accelerators & Servers to Edge Devices: A Comprehensive Memory Portfolio<\/h3>\n
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The SK hynix exhibition booth was likewise designed to offer an at-a-glance view of the key memory solutions playing an active role across AI systems. The booth was organized into several zones \u2014 the Partnership Zone, The Smart Edge, Next-Generation Tech, and Technical Session \u2014 each drawing a steady stream of visitors eager to see SK hynix\u2019s technology capabilities and vision for the future.<\/p>\n

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\u25b2 Visitors examining the HBM4 model and the Vera Rubin model in the Partnership Zone<\/p>\n

The Partnership Zone focused on highlighting SK hynix\u2019s solid collaborative relationships with major tech leaders driving the evolution of AI technology, such as NVIDIA and Dell, along with the technology capabilities that make these partnerships possible. On the right side of the display, an HBM4 model and a model of NVIDIA\u2019s next-generation AI accelerator, Vera Rubin, were placed side by side, intuitively illustrating how the two companies\u2019 technologies come together.<\/p>\n

Alongside them, physical units of the 12-layer 48GB HBM4E, 16-layer 48GB HBM4, 12-layer 36GB HBM3E, and SOCAMM2*<\/span> were arranged in sequence, allowing visitors to see firsthand the irreplaceable technology leadership SK hynix has built together with its key partners.<\/p>\n

*<\/span> SOCAMM2 (Small Outline Compression Attached Memory Module): A memory module based on low-power DRAM and specialized for AI servers \u2014 a memory module form factor optimized for AI servers. SK hynix has announced mass production of the 192GB SOCAMM2, which applies 1cnm-based LPDDR5X.<\/p>\n

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\u25b2 Dell\u2019s \u2018R7625\u2019 server system and SK hynix\u2019s \u201864GB DDR5 RDIMM\u2019 server DRAM<\/p><\/div><\/a>

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On the left side of the display, Dell\u2019s \u2018R7625\u2019 server system \u2014 a leader in the global AI server market \u2014 was exhibited together with the SK hynix server DRAM \u201864GB DDR5 RDIMM*<\/span>\u2019 and eSSD \u2018PS1110 E3.S\u2019 installed within it. Flanking it were SK hynix\u2019s key server DRAM products \u2014 including the high-capacity \u2018256GB DDR5 RDIMM*<\/span>\u2019 suited to AI workloads and the \u2018128GB DDR5 RDIMM\u2019 known for its high bandwidth \u2014 displayed alongside SK hynix\u2019s flagship eSSD lineup, including the PEB210 E1.S 9.5mm, PEB210 M.2 2280, and PS1101 E3.S, so that visitors could compare their specifications and performance.<\/p>\n

In particular, the PS1101 high-capacity eSSD lineup is a QLC-based product that delivers about 55% higher performance than the previous 176-layer generation, and is being developed sequentially by form factor. The company plans to begin sample shipments to major CSP customers starting in August 2026. Through this, SK hynix aims to further strengthen its high-capacity NAND leadership in the AI data center market.<\/p>\n

*<\/span> RDIMM (Registered Dual In-line Memory Module): A server module that combines multiple DRAM chips.
\n*<\/span> MRDIMM (Multiplexed Rank Dual In-line Memory Module): A product that significantly boosts speed by operating two ranks \u2014 the module\u2019s basic unit of operation \u2014 simultaneously.<\/p>\n

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\u25b2 SK hynix\u2019s \u2018375-layer 4D NAND Wafer\u2019, \u2018375-layer 1Tb TLC 154B 32DP\u2019 and \u2018375-layer 1Tb TLC 334B QDP\u2019<\/p>\n

Located directly behind the Partnership Zone, \u2018The Smart Edge\u2019 presented a portfolio of the latest NAND products featuring cutting-edge technology, along with products for edge devices. Among the products on display, the \u2018375-layer 4D NAND Wafer\u2019 at the center was the first to catch the eye. As SK hynix\u2019s first NAND product to apply wafer bonding, it delivers both high performance and low power consumption, giving it broad utility across a wide range of device environments, including AI data centers.<\/p>\n

Below it, the \u2018375-layer 1Tb TLC*<\/span> 154B 32DP\u2019 \u2014 the first TLC-based product to support a 2-Channel*<\/span> 32-Die Package*<\/span>11 \u2014 was displayed alongside the \u2018375-layer 1Tb TLC 334B QDP*<\/span>\u2019, which improves space efficiency with a smaller footprint (13.5 \u00d7 12.5 mm) than a conventional 4-Channel Package*<\/span> (14 \u00d7 18 mm), allowing visitors to take in SK hynix\u2019s cutting-edge NAND and packaging technology at a glance.<\/p>\n

The 375-layer 4D NAND is characterized by 2.5 times higher performance per watt than the previous generation, making it optimized for AI infrastructure environments such as data centers that require both power efficiency and performance. Building on it, SK hynix plans to begin mass production of high-performance eSSD (enterprise SSD) in the first half of next year, and is preparing to commercialize a range of specialized features \u2014 including IOPS (input\/output operations per second) optimization, high bandwidth, and Adaptive Media Storage*<\/span> \u2014 in collaboration with customers to meet the demands of AI data centers.<\/p>\n

*<\/span> TLC: NAND is classified by the number of bits that can be stored per cell \u2014 SLC (Single Level Cell, 1 bit), MLC (Multi Level Cell, 2 bits), TLC (Triple Level Cell, 3 bits), and QLC (Quadruple Level Cell, 4 bits). The more information stored, the more data can be held within the same area.
\n*<\/span> Channel: An independent communication path through which the chip and controller exchange data within a NAND package.
\n*<\/span> 32-Die Package: A packaging technology that stacks 32 NAND dies within a single package to substantially increase capacity.
\n*<\/span> QDP (Quad Die Package): A packaging technology that stacks four dies.
\n*<\/span> 4-Channel Package: A standard NAND packaging technology with four independent channels.
\n*<\/span> Adaptive Media Storage: A cloud-based or hybrid system that automatically expands capacity, adjusts performance, and optimizes cost for large media files such as video and audio according to real-time workflow demands.<\/p>\n

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\u25b2 SK hynix\u2019s SSD lineup<\/p><\/div><\/a>

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\u25b2 SK hynix\u2019s LPDDR and UFS lineup<\/p><\/div><\/a>

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On the back display, SK hynix introduced its fifth-generation PCIe*<\/span>-based SSD lineup \u2014 including the PCB01, PVF01, and PQF02 \u2014 alongside LPDDR*<\/span> and UFS*<\/span> products in various specifications.<\/p>\n

SK hynix plans to address the AI edge inference market by applying data-processing methods optimized for it \u2014 such as data-aware placement and media-aware tiering \u2014 in its mobile and cSSD products.<\/p>\n

In particular, the latest products \u2014 including LPDDR6, LPDDR5\/5X, and UFS 4.1, UFS 5.0 which can process large volumes of data without errors or delays even in the low-power environments of battery-powered edge devices \u2014 were presented as core memory solutions for implementing Physical AI*<\/span> technology, drawing keen interest from industry professionals throughout the exhibition.<\/p>\n

*<\/span> PCIe (Peripheral Component Interconnect Express): A high-speed serial input\/output interface used on the mainboards of digital devices.
\n*<\/span> LPDDR: The latest mobile DRAM product characterized by low-power operation. The \u2018LP\u2019 (Low Power) prefix denotes this line, which has been developed across generations: LPDDR \u2192 LPDDR2 \u2192 LPDDR3 \u2192 LPDDR4 \u2192 LPDDR4X \u2192 LPDDR5 \u2192 LPDDR5X \u2192 LPDDR6.
\n*<\/span> UFS (Universal Flash Storage): A universal storage product capable of reading and writing simultaneously. Widely used in mobile devices for its low power consumption, high performance, and high reliability.
\n*<\/span> Physical AI: AI applied to physical systems such as robots, autonomous vehicles, and smart manufacturing equipment.<\/p>\n

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Demonstrating CXL-Based Next-Generation Memory Technology, Proving Its Firm Technology Leadership<\/h3>\n
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The zone that drew the most enthusiastic interest during the event was \u2018Next-Generation Tech.\u2019 Here, SK hynix demonstrated CXL-based next-generation memory technology, capturing the strong attention of visitors to the booth.<\/p>\n

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\u25b2 A demonstration of SK hynix\u2019s ReAct AI Agent Serving technology using Pooled Memory<\/p>\n

First, the ReAct (Reasoning and Acting) AI Agent Serving demo presented a distributed AI Agent Serving system that connects multiple servers and GPUs using Pooled Memory*<\/span>. Through this, SK hynix demonstrated that transferring or reusing the KV cache*<\/span> on the basis of CXL Pooled Memory can significantly improve the performance of an AI Agent Serving system compared with legacy systems that rely on network communication.<\/p>\n

* <\/span>Pooled Memory: A technology that groups multiple CXL memory units into a pool, allowing several hosts to effectively share its capacity and thereby raising overall memory utilization.
\n*<\/span> KV Cache (Key Value Cache): Temporary memory that stores previously computed results as a large language model-based AI agent generates text. It grows exponentially as conversations lengthen and workloads increase, so the memory capability to store and process it efficiently has a significant impact on an AI agent\u2019s performance.<\/p>\n

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\u25b2 A demonstration of SK hynix\u2019s ReAct AI Agent Serving technology using CMM-Hybrid<\/p>\n

SK hynix also demonstrated the same ReAct AI Agent Serving system using CMM-Hybrid*<\/span>, confirming that the implemented system can efficiently store and rapidly reuse the large volumes of KV cache generated on an ongoing basis. In particular, the demonstration showcased both the ability to quickly predict the KV cache needed based on prior conversation and task history, and the performance to prefetch the required KV cache into DRAM for rapid processing. It also proved that storing the entire KV cache on SSD can deliver fast read performance and large-capacity storage at the same time.<\/p>\n

*<\/span> CMM-Hybrid: A CXL-based hybrid memory solution that combines DRAM and SSD.<\/p>\n

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\u25b2 A demonstration of SK hynix\u2019s \u2018Efficient Long Context LLM Serving\u2019 technology<\/p>\n

In addition, SK hynix demonstrated \u2018Efficient Long Context LLM Serving,\u2019 a next-generation AI inference system that can enhance the performance of LLMs*<\/span>. Using CMM-Ax, which embeds computing capabilities within memory, SK hynix presented a new approach to efficiently accelerating the \u2018long-context*<\/span>\u2019 of LLMs \u2014 something that has been difficult to handle on legacy GPU-based systems \u2014 demonstrating strong potential for use in real-world AI infrastructure. In fact, the research behind these results was accepted by MICRO 2026, the most prestigious conference in the field of computer architecture, formally recognizing its technical excellence.<\/p>\n

* <\/span>LLM (Large Language Model): An artificial intelligence model that learns from big data to generate and understand natural, human-like sentences. By greatly increasing the scale of its parameters, it acquires advanced language-processing capabilities such as complex context comprehension, reasoning, and translation.
\n* <\/span>Long-context: The range of text an AI can process at once is defined as context. The longer the context, the more information can be referenced at once to generate a sophisticated response \u2014 but this also requires greater memory capacity.<\/div>\n

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\u25b2 Tech Session underway at the SK hynix exhibition booth<\/p><\/div><\/a>

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At the innermost part of the booth, a dedicated space allowed visitors to revisit 5 of the 12 Technical Session presentations delivered by SK hynix.<\/p>\n

On the first day, Technical Leader Cho Min-jeong of Diffusion Technology presented on the theme \u2018Autonomous Fab Journey: From AI-Assisted Decisions to Agentic Manufacturing.\u2019 On the second day, Technical Leader Kim Kyoung-tae of eSSD Quality Engineering took the stage with \u2018Beyond Air Cooling: Assessing the Stability SSD in Immersion Cooling,\u2019 followed by Team Leader Joh Jung-hyun of Solution Development presenting \u2018Why, What, How HBF?\u2019 On the final day, Technical Leader Hwang Min-soon of Solution Development presented \u2018New Era of Memory Scalability and Expansion based on Chiplet for AI-driven Memory Applications,\u2019 and Team Leader Shim Eung-bo of Next-Gen Product Planning took the stage with \u2018Approach to AI domain using CXL pooling.\u2019<\/p>\n

SK Hynix commented, \u201cThrough FMS 2026, we presented the direction for next-generation AI memory architectures and highlighted our technical leadership across the entire AI infrastructure spectrum\u2014from HBM and server DRAM to NAND and CXL. We will continue to proactively develop and supply optimal AI memory solutions tailored to the needs of our customers and partners.\u201d<\/p>\n

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