{"id":13363,"date":"2026-09-28T14:23:44","date_gmt":"2026-09-28T05:23:44","guid":{"rendered":"https:\/\/news.skhynix.com\/en\/?p=13363"},"modified":"2026-09-28T14:23:44","modified_gmt":"2026-09-28T05:23:44","slug":"tsmc-oip-conference-2026","status":"publish","type":"post","link":"https:\/\/news.skhynix.com\/en\/tsmc-oip-conference-2026\/","title":{"rendered":"\u201cBehind AI\u2019s Rapid Growth Lies Memory\u201d \u2014 SK hynix Shares Its Next-Generation Memory Portfolio at the TSMC OIP Conference"},"content":{"rendered":"

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At the TSMC Open Innovation Platform(OIP) Conference, held on the 23rd(local time) in Santa Clara, California, US, SK hynix shared its next-generation memory portfolio and development strategy, and reaffirmed its solid partnership with TSMC by receiving the Partner of the Year Award for the second consecutive year.<\/p>\n

OIP is an open innovation platform operated by TSMC to develop technologies and collaborate with the companies that together make up the semiconductor ecosystem. Each year in the second half, TSMC invites OIP member companies and major customers to its ecosystem forums held around the world, fostering active technological exchange. SK hynix has taken part in the OIP Forums since 2024, introducing its evolving AI memory technology capabilities developed through its strategic partnership with TSMC.<\/p>\n

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\u25b2 Visitors explore SK hynix\u2019s exhibition booth<\/p><\/div><\/a>

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\u25b2 Visitors explore SK hynix\u2019s exhibition booth<\/p><\/div><\/a>

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In today\u2019s AI semiconductor ecosystem, collaboration between companies has grown closer than ever. The era in which design and manufacturing, memory and logic were each optimized within their own domains has given way to an approach in which companies design and validate together from the earliest stages. Held amid this shift, this year\u2019s TSMC OIP Conference offered an opportunity to examine the latest technology development trends and explore new opportunities for collaboration. SK hynix, for its part, focused on showcasing its technological capabilities and product lineup while further defining and expanding its collaborative relationships with TSMC and other key partners.<\/p>\n

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Meeting SK hynix Inside the Superchip \u2014 Demonstrating HBM Capabilities That Have Advanced Alongside AI<\/h3>\n
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\u25b2 The SK hynix booth design, carrying a message that emphasizes the importance of memory in the AI era<\/p>\n

SK hynix presented \u201cThe Memory behind the Intelligence at Scale\u201d as the slogan for this exhibition. The message captured the industrywide trend in which AI technology is advancing and its fields of application are rapidly expanding, while emphasizing that sustaining this growth depends on the support of memory technology. This message was reflected in the exhibition\u2019s composition as well, which presented a range of memory solutions across different layers \u2014 from HBM*<\/span> to server DRAM and eSSD \u2014 that support AI computation and data storage.<\/p>\n

* <\/span>HBM(High Bandwidth Memory): A high-value, high-performance product that vertically connects multiple DRAM chips to increase capacity and dramatically enhance data processing speed. HBM has been developed in sequence: 1st generation(HBM), 2nd generation(HBM2), 3rd generation(HBM2E), 4th generation(HBM3), 5th generation(HBM3E), and 6th generation(HBM4)<\/div>\n

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\u25b2 NVIDIA\u2019s superchip \u201cVera Rubin,\u201d equipped with SK hynix\u2019s 12-layer 36GB HBM4 and 96GB SOCAMM2<\/p>\n

The product exhibition was organized into two main display stands: HBM and AI-optimized Memory and Storage. On the HBM stand, which visitors encountered immediately to their right upon entering the booth, NVIDIA\u2019s superchip \u201cVera Rubin\u201d was displayed together with SK hynix\u2019s 12-layer 36GB HBM4 and 96GB SOCAMM2*<\/span> mounted on it, so visitors could examine them closely. Alongside it, explanatory text detailing the role of the SK hynix products within Vera Rubin helped deepen visitors\u2019 understanding.<\/p>\n

* <\/span>SOCAMM2(Small Outline Compression Attached Memory Module2): A memory module specialized for AI servers, based on low-power DRAM<\/div>\n

In practice, the 12-layer 36GB HBM4 is integrated directly around the Rubin GPU core, serving as a high-bandwidth data pathway that resolves the data transfer latency arising in complex matrix operations. SOCAMM2, meanwhile, operates as the main system memory for the Vera CPU, supporting the complex computational processes and the resulting data movement so that AI agents can immediately reflect the context of long conversations in their responses.<\/p>\n

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\u25b2 SK hynix\u2019s key HBM lineup and the 192GB SOCAMM2 featured in this exhibition<\/p><\/div><\/a>

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\u25b2 SK hynix\u2019s key HBM lineup and the 192GB SOCAMM2 featured in this exhibition<\/p><\/div><\/a>

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Around the superchip, key HBM products \u2014 the 12-layer 48GB HBM4E, the 16-layer 48GB HBM4, and the 12-layer 36GB HBM3E \u2014 were arranged side by side with an actual 192GB SOCAMM2 unit. By comparing the products already mounted in an AI accelerator with the next-generation lineup displayed beside them, visitors could see firsthand
\nSK hynix\u2019s HBM capabilities, which have steadily evolved in step with the advancement of AI technology.<\/p>\n

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From Server DRAM to SSD \u2014 Unveiling a Next-Generation Product Lineup for the AI Infrastructure Market<\/h3>\n
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\u25b2 SK hynix\u2019s next-generation server DRAM lineup featured in this exhibition<\/p>\n

On the left side of the booth, a display stand was arranged so visitors could view the next-generation server DRAM and SSD lineups in one place. The server DRAM lineup included the \u201c256GB 3DS*<\/span> RDIMM*<\/span>,\u201d which achieves the industry\u2019s largest capacity tailored to AI workloads, along with the high-bandwidth \u201c128GB MRDIMM*<\/span>\u201d and the \u201c64GB RDIMM,\u201d the world\u2019s first to apply a 10-nanometer(nm) class sixth-generation(1c)*<\/span> process.<\/p>\n

* <\/span>3DS(3D Stacked Memory): High-performance memory that connects two or more DRAM chips using TSV(Through-Silicon Via)
\n* <\/span>RDIMM(Registered Dual In-line Memory Module): A server memory module composed of multiple DRAM chips
\n* <\/span>MRDIMM(Multiplexed Rank Dual In-line Memory Module): A product with significantly enhanced speed achieved by operating two ranks \u2014 the module\u2019s basic operating units \u2014 simultaneously
\n* <\/span>The 10-nanometer(nm) class process technology has progressed sequentially through generations 1x, 1y, 1z, 1a, 1b, and 1c(sixth generation)<\/div>\n
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\u25b2 SK hynix\u2019s SSD lineup featured in this exhibition<\/p><\/div><\/a><\/div>\n<\/div>\n

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\u25b2 SK hynix\u2019s SSD lineup featured in this exhibition<\/p><\/div><\/a><\/div>\n<\/div>\n

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\u25b2 SK hynix\u2019s SSD lineup featured in this exhibition<\/p><\/div><\/a><\/div>\n<\/div>\n<\/div>\n

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The SSD stand featured a lineup spanning different form factors and use environments \u2014 the PEB210 E1.S, the PS1101 E3.S, and the PEB210 M.2 \u2014 demonstrating SK hynix\u2019s storage solution capabilities to meet a wide range of customer needs. The \u201cPEB210 E1.S,\u201d which supports Direct Liquid Cooling(DLC), drew strong interest from customers operating data centers, while the \u201cPS1101 E3.S,\u201d SK hynix\u2019s first QLC*<\/span>-based eSSD, prompted a steady stream of inquiries from enterprise customers.<\/p>\n

* <\/span>QLC: NAND is classified by the number of bits that can be stored per cell \u2014 SLC(Single Level Cell, 1 bit), MLC(Multi Level Cell, 2 bits), TLC(Triple Level Cell, 3 bits), and QLC(Quadruple Level Cell, 4 bits). The greater the amount of information stored, the more data can be held in the same area<\/div>\n

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\u25b2 A visitor at the SK hynix booth inquiring about detailed product information<\/p>\n

Throughout the exhibition, SK hynix\u2019s booth saw a constant flow of industry professionals eager to take a closer look at the AI memory solutions that form a core pillar of AI infrastructure. Company representatives also continued to visit to review SK hynix\u2019s development plans and current technological capabilities, and to propose new collaborations on that basis.<\/p>\n

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Winning \u201cPartner of the Year\u201d for the Second Consecutive Year in Recognition of the HBM5 and CoWoS Collaboration<\/h3>\n
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\u25b2 (From left) Team Leader Jinwoo Park (PKG Product TE) and Vice President Jaesik Lee (Head of Advanced PKG Research), receiving the Partner of the Year Award on behalf of SK hynix at the TSMC OIP Conference<\/p>\n

At this forum, SK hynix was named a Partner of the Year Award winner in the \u201c3DFabric-HBM Integration\u201d category. This marked the company\u2019s second consecutive win following last year, this time in recognition of a collaboration that validated HBM5 on the basis of TSMC\u2019s CoWoS*<\/span> to advance next-generation AI systems.<\/p>\n

* <\/span>CoWoS(Chip on Wafer on Substrate): TSMC\u2019s 2.5D advanced packaging technology, used to integrate multiple chips such as HBM and GPUs onto a single substrate to build high-performance AI accelerators<\/div>\n

As HBM advances through successive generations, raising its stack count and bandwidth, fully realizing these gains in performance requires close coordination with the advanced packaging technology that integrates it into an actual AI accelerator. It was here that
\nSK hynix\u2019s Package Development organization and TSMC carried out validation together from the earliest stages, laying the foundation for next-generation AI systems \u2014 a collaborative relationship that led to this award.<\/p>\n

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From the Role of PCIe in the AI Era to the Next-Generation SSD Roadmap \u2014 Sharing a Vision for Technology Development in the Presentation Session<\/h3>\n
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\u25b2 Daesik Park, a distinguished engineer in PCIe Design, delivers a presentation<\/p>\n

In the presentation session, Daesik Park, a distinguished engineer in PCIe Design took the stage as the second speaker in a joint presentation with Cadence, sharing changing market trends and SK hynix\u2019s response under the theme \u201cPCI Express Solutions for HPC\/AI Storage,\u201d and introducing the AI memory technologies being developed to address them.<\/p>\n

Park first outlined the technological shifts underway in the PCIe*<\/span> field. \u201cSince the fourth generation, a new generation has arrived every two to three years, doubling bandwidth each time, and from the sixth generation in particular, power optimization and collaboration between design and process have become even more important,\u201d he explained. \u201cAs new memory layers \u2014 including HBM and HBF*<\/span> \u2014 take shape to improve AI and GPU performance, PCIe has emerged as the key interface connecting these layers to GPUs, CPUs, and networks.\u201d<\/p>\n

* <\/span>PCIe(Peripheral Component Interconnect Express): A high-speed serial input\/output interface used on the mainboards of digital devices
\n* <\/span>HBF(High Bandwidth Flash): A next-generation NAND-based memory technology being discussed as a new memory layer between HBM and SSD. Like HBM, it applies a logic process to the base die, providing far greater capacity than HBM while securing comparable bandwidth and cost efficiency<\/div>\n

He also shared market projections and SK hynix\u2019s response. \u201cAs AI infrastructure expands, the PCIe-based eSSD market is expected to grow roughly 3.8 times, from 509EB*<\/span> in 2026 to 1,933EB in 2030,\u201d Park said. \u201cAs demand grows for high capacity, high density, and cooling efficiency, demand for the E1.S and E3 form factors will also rise rapidly.\u201d He continued: \u201cSK hynix has developed a wide range of SSD controllers using TSMC processes since third-generation PCIe, and for the sixth and seventh generations we are preparing next-generation SSD solutions based on chiplets*<\/span>. The design separates the conventional single-chip controller into chiplet*<\/span> units connected via UCIe*<\/span>, which is expected to enable shorter development times, independent generation transitions for each function, capacity expansion, and power optimization.\u201d<\/p>\n

* <\/span>EB(Exabyte): A unit of data capacity; 1EB(exabyte) equals 1 million TB(terabytes)
\n* <\/span>Chiplet: A technology that divides one large chip by function into several smaller chips, then connects them within a single package. Because each function can be developed and combined independently, it shortens development time and enhances design flexibility
\n* <\/span>UCIe(Universal Chiplet Interconnect Express): An open standard interface for connecting different chiplets within a single package<\/div>\n

SK hynix stated, \u201cBy winning the Partner of the Year Award for the second consecutive year at this OIP Conference, we once again confirmed the results of the collaboration we have built with TSMC.\u201d The company added, \u201cWe will continue to work closely with a range of partners to create the memory solutions the AI era demands.\u201d<\/p>\n","protected":false},"excerpt":{"rendered":"

At the TSMC Open Innovation Platform(OIP) Conference, held on the 23rd(local time) in Santa Clara, California, US, SK hynix shared its next-generation memory portfolio and development strategy, and reaffirmed its solid partnership with TSMC by receiving the Partner of the<\/p>\n","protected":false},"author":23,"featured_media":13389,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"_migrated_source_id":0,"footnotes":"","_members_access_role":[],"_members_access_error":""},"categories":[5],"tags":[1373,25,16,13,24,115,1623],"class_list":["post-13363","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-tech-and-ai","tag-ai-semiconductor","tag-essd","tag-hbf","tag-hbm","tag-socamm2","tag-ssd","tag-tsmc-oip"],"acf":[],"_links":{"self":[{"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/posts\/13363","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/users\/23"}],"replies":[{"embeddable":true,"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/comments?post=13363"}],"version-history":[{"count":10,"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/posts\/13363\/revisions"}],"predecessor-version":[{"id":13405,"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/posts\/13363\/revisions\/13405"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/media\/13389"}],"wp:attachment":[{"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/media?parent=13363"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/categories?post=13363"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/tags?post=13363"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}