{"id":13620,"date":"2026-10-16T09:00:16","date_gmt":"2026-10-16T00:00:16","guid":{"rendered":"https:\/\/news.skhynix.com\/en\/?p=13620"},"modified":"2026-10-16T09:10:57","modified_gmt":"2026-10-16T00:10:57","slug":"ocp-global-summit-2026","status":"publish","type":"post","link":"https:\/\/news.skhynix.com\/en\/ocp-global-summit-2026\/","title":{"rendered":"\u201cMemory-Centric Server Systems Are the Future\u201d: SK hynix Presents Its Next-Generation AI Infrastructure Vision at OCP Global Summit 2026"},"content":{"rendered":"

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As the volume of data handled by AI grows explosively, data bottlenecks have emerged as a new challenge. Can next-generation memory technology offer the solution? There is now an opportunity to hear SK hynix\u2019s answer to this question.<\/p>\n

SK hynix took part in OCP Global Summit 2026, held from the 12th to the 15th in San Jose, California, where it unveiled a wide range of next-generation memory solutions and presented the direction memory technology should take in the AI era.<\/p>\n

OCP Global Summit is a technology conference for sharing and standardizing the design and specifications of data center hardware. This year, with the infrastructure technologies that will underpin the advancement of AI emerging as a central theme, the new server system proposed by SK hynix drew considerable attention. SK hynix demonstrated the next-generation solutions it is preparing for servers at the actual system level, proving their feasibility and once again affirming its technological leadership.<\/p>\n

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Proposing a Next-Generation Server System Based on \u2018CXL Pooled Memory\u2019\u2026 Confirming the Benefits Through Live Demos<\/h3>\n
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\u25b2 SK hynix\u2019s exhibition booth<\/p>\n

With a booth concept that balanced a sturdy gray frame with neon-blue lighting, SK hynix gave visual form to \u2018reliability\u2019 and \u2018efficiency\u2019\u2014the core values of its next-generation memory solutions. The exhibition space was divided into front and rear sections. At the front, a \u2018Memory Section\u2019 showcasing the company\u2019s current flagship products captured visitors\u2019 attention, while the spacious \u2018System Demo\u2019 section at the rear allowed visitors to take a closer look at the SK hynix memory solutions that will make up the next-generation server ecosystem.<\/p>\n

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\u25b2 Visitors touring the \u2018System Demo\u2019 section<\/p>\n

The \u2018System Demo\u2019 section introduced three solutions in sequence, from left to right: CMM-DDR5, MARS, and CMM-Ax. CMM (CXL* Memory Module)-DDR5 is a memory solution that improves resource utilization efficiency by having multiple servers share a memory pool and use as much of it as they need, based on the CXL interface standard. At this exhibition, SK hynix unveiled its second-generation product (256GB), optimized for AI workloads and based on CXL 3.2. Compared with the previous generation, the product more than doubles bandwidth (80GB\/s) and improves energy efficiency by about 30%. With CXL Pooled functionality also applied, it is drawing attention as a next-generation memory product that will effectively resolve bottlenecks in data-intensive, high-load environments.<\/p>\n

* <\/span>CXL (Compute eXpress Link): A next-generation solution that efficiently connects CPUs, GPUs, memory, and other components within a computing system to support large-capacity, ultra-high-speed computation. Based on the PCIe interface, it offers fast data transfer and provides a pooling function that uses memory efficiently.<\/div>\n

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\u25b2 Visitors examining the CMM-DDR5 product<\/p>\n

In September last year, SK hynix signed a business agreement with NAVER Cloud and has since been working jointly to resolve bottlenecks in cloud AI services using CXL-based memory solutions. At this demo, the company presented the results of validating\u2014at the PoC* level\u2014whether a KV cache*-sharing solution in an agentic AI* environment and an embedding-sharing solution in \u2018OmniServe\u2019, an omni-modal* service, actually work. Having analyzed real customer systems and workloads to confirm the applicability of its CXL-based solutions, SK hynix has laid the groundwork for a full-scale expansion of these solutions.<\/p>\n

* <\/span>Agentic AI: AI that sets its own goals and carries out multi-step tasks without user instructions.
\n* <\/span>KV Cache (Key Value Cache): Temporary memory that stores previously computed results when a large language model-based AI agent generates text. It grows exponentially the longer a conversation becomes and the more tasks there are to process, so the ability to store and process it efficiently has a major impact on an AI agent\u2019s performance.
\n* <\/span>Omni-Modal: An approach that processes multiple forms of data\u2014such as text, images, and voice\u2014together within a single model.
\n* <\/span>PoC (Proof of Concept): A stage that verifies whether a new technology or concept actually works.<\/div>\n

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\u25b2 Visitors reviewing information about MARS<\/p>\n

MARS (Memory Centric AI Rack System) is a next-generation system that maximizes efficiency by integrating partners\u2019 solutions into a single rack*, with memory at its core. At this exhibition, SK hynix presented three demos together with several partners.<\/p>\n

* <\/span>Rack: A standard-sized frame used in data centers to stack servers, storage, network equipment, and other devices in layers. Because equipment is managed in rack units, the rack serves as the basic building block of data center infrastructure.<\/div>\n

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\u25b2 A demonstration of AI agent serving technology using CXL pooled memory<\/p>\n

In the AI agent serving demo, SK hynix\u2014together with Arcee, Liqid, and Marvell\u2014demonstrated a system that connects multiple servers and GPUs using pooled memory*. Through this, the company proved that transferring or reusing a KV cache based on CXL pooled memory significantly improves system performance compared with conventional methods that rely on network communication.<\/p>\n

* <\/span>Pooled Memory: Technology that groups multiple CXL memory units into a pool and raises overall memory utilization by allowing several hosts to effectively share its capacity.<\/div>\n

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\u25b2 A demonstration of AI agent serving technology using CXL hybrid memory<\/p>\n

In a demo conducted with AMD, Penguin, Xcena, and Arcee, SK hynix showed the effectiveness of a memory rack using CXL memory and CXL hybrid memory*. The results confirmed that the memory rack can efficiently store and rapidly reuse the large-scale KV caches that are continuously generated. In particular, the demo clearly showed two capabilities: quickly predicting which KV caches will be needed based on prior conversation and task history, and loading the required KV caches into DRAM in advance for fast processing. It also proved that, by storing the full KV cache on an SSD, the rack can deliver both fast read performance and high-capacity storage at the same time.<\/p>\n

* <\/span>CXL Hybrid Memory: A CXL-based hybrid memory solution that combines DRAM and SSD.<\/div>\n

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\u25b2 A demonstration of technology that reduces service response latency using pooled memory<\/p>\n

With Pickle, a personal AI agent service provider, SK hynix carried out a demo that reduces service response latency using pooled memory. The demonstration confirmed that streaming based on pooled memory can accelerate the data transfers between the multiple AI models essential to a personal AI agent, so that final results reach users more quickly.<\/p>\n

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\u25b2 A demonstration of Efficient Long Context LLM Serving technology<\/p>\n

CMM-Ax is a next-generation memory solution that combines computation functions with memory. By performing computations directly inside the memory, without moving data, it can reduce the power and cost burden on data centers. At this exhibition, through a demo of its next-generation AI inference system, \u2018Efficient Long Context* LLM* Serving\u2019, SK hynix showed that CMM-Ax can efficiently accelerate the long contexts that have been difficult to process on conventional GPU-based systems. The research behind these achievements was also officially recognized for its technical excellence, having been published to \u2018MICRO 2026\u2019, the most prestigious academic conference in the field of computer architecture.<\/p>\n

* <\/span>Long Context: The range of text that AI can process at once is defined as its context. The longer the context, the more information AI can reference at once to generate refined answers\u2014but this also requires more memory capacity.
\n* <\/span>LLM (Large Language Model): An AI model that learns from big data to generate and understand natural, human-like sentences. By greatly increasing the scale of its parameters, it acquires advanced language-processing capabilities such as complex context comprehension, reasoning, and translation.<\/div>\n
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Sharing Its Product Portfolio from HBM to HBF, \u2026 The Present and Future of Memory Technology in One Place<\/h3>\n
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The Memory Section was arranged so that visitors could see the flagship products with which SK hynix is currently leading the memory market. In the product portfolio exhibition space at the far left, a lineup of products for AI infrastructure\u2014spanning eSSDs and server DRAM\u2014was on display.<\/p>\n

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\u25b2 SK hynix\u2019s main eSSD products<\/p><\/div><\/a>

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\u25b2 SK hynix\u2019s main server DRAM products<\/p><\/div><\/a>

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The eSSD lineup presented products with different uses tailored to diverse customer needs, organized by form factor: the high-performance \u2018PS1010 U.2\u2019; the high-performance \u2018PS1110 E3.S\u2019 and high-capacity \u2018PS1101 E3.S\u2019 currently under sequential development; and the \u2018PEB210 E1.S\u2019 and \u2018PEB210 M.2 2280\u2019, which support Direct Liquid Cooling (DLC) and are drawing attention as eSSDs for data centers.<\/p>\n

For server DRAM, SK hynix introduced a DDR5 RDIMM lineup in a range of capacities\u2014led by the \u2018256GB 3DS* RDIMM*\u2019, which delivers the industry\u2019s largest capacity for AI workloads, and extending to 96GB and 64GB. Alongside the 128GB DDR5 MRDIMM*, it also exhibited the \u2018192GB SOCAMM*2\u2019, which improves power and space efficiency with a new form factor.<\/p>\n

* <\/span>3DS (3D Stacked Memory): High-performance memory that connects two or more DRAM chips with TSVs (through-silicon vias).
\n* <\/span>RDIMM (Registered Dual In-line Memory Module): A server module that combines multiple DRAM chips.
\n* <\/span>MRDIMM (Multiplexed Rank Dual In-line Memory Module): A product in which two ranks\u2014the basic operating unit of a module\u2014operate simultaneously, dramatically improving speed.
\n* <\/span>SOCAMM (Small Outline Compression Attached Memory Module): A low-power DRAM-based memory module specialized for AI servers.<\/div>\n

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\u25b2 A touchscreen where visitors can check product information<\/p>\n

SK hynix also set up a touchscreen model resembling an actual server, allowing visitors to check detailed product information.<\/p>\n

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\u25b2 A visitor mounting SK hynix\u2019s HBM4 product onto NVIDIA\u2019s Vera Rubin model<\/p>\n

The HBM* exhibition space in the center was designed so that visitors could take in both SK hynix\u2019s HBM technology leadership and its solid partnership with NVIDIA at a glance. On the left side of the display, a model of NVIDIA\u2019s Vera Rubin superchip highlighted the partnership between the two companies, while visitors could mount HBM4 and SOCAMM2 onto a server model themselves. On the right stood an HBM model magnified one million times, with an accompanying monitor playing a video on TSV* and Advanced MR-MUF*\u2014the core technologies behind HBM. Between the two models, the actual HBM4E, HBM4, and HBM3 products were placed so that visitors could see firsthand how HBM products have evolved from generation to generation.<\/p>\n

* <\/span>HBM (High Bandwidth Memory): A high-value-added, high-performance product that connects multiple DRAM chips vertically to increase capacity and dramatically raise data processing speed. HBM has been developed in the following order: 1st generation (HBM) \u2013 2nd generation (HBM2) \u2013 3rd generation (HBM2E) \u2013 4th generation (HBM3) \u2013 5th generation (HBM3E) \u2013 6th generation (HBM4) \u2013 7th generation (HBM4E).
\n* <\/span>TSV (Through Silicon Via): Technology that connects chips vertically through electrodes that pass straight through the silicon substrate.
\n* <\/span>Advanced MR-MUF: A next-generation MR-MUF technology that applies warpage control\u2014a chip-control technology that stacks chips 40% thinner than conventional chips without bending\u2014and also improves heat dissipation.<\/div>\n

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\u25b2 A model showing the structure of HBF<\/p>\n

HBF (High Bandwidth Flash) is a next-generation NAND solution that, like HBM, applies TSV technology to combine the high capacity of conventional storage with high bandwidth. As the inference-centric agentic AI era unfolds, it is drawing attention as a key technology for efficiently handling the surging data usage of AI. On the left side of the display stood a model showing the structure of HBF, with a banner introducing its detailed specifications to its right. On an accompanying monitor and tablet, SK hynix introduced the key features of HBF, along with the respective strengths of HBM and HBF across different AI inference service environments, through videos and performance graphs based on internal simulations. It showed that HBM\u2019s high-speed processing can be leveraged in environments where fast response times are critical, while HBF\u2019s high-capacity characteristics can be leveraged in environments that require large-capacity memory to serve many users.<\/p>\n

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\u25b2 A graphic conveying SK hynix\u2019s vision, located on the outer wall of the booth<\/p>\n

Meanwhile, a graphic conveying the company\u2019s vision of providing optimized solutions across the entire memory hierarchy was displayed on the right wall of the booth. Beneath the journey from developing the world\u2019s first HBM in 2013 to achieving its current technological leadership, the latest products and technology development status in each of the HBM, DRAM, and NAND fields were also introduced.<\/p>\n

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\u201cWe Will Break Through Technological Limits with a Memory-Centric, Next-Generation AI Rack System\u201d<\/h3>\n
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\u25b2 Vice President Hosik Kim, head of the Memory Systems Research department, during his presentation<\/p>\n

Alongside the exhibition, the presentation sessions also heightened expectations for memory-centric server systems. First, in the \u2018Executive\u2019 session held on the afternoon of the first day, Vice President Hosik Kim, head of the Memory Systems Research, took the stage as a speaker and gave a presentation titled \u2018Introduction to Memory-centric AI Rack Systems (MARS)\u2019.<\/p>\n

Vice President Kim first noted that, as generative AI and hyperscale data centers grow rapidly, conventional CPU- and GPU-centric architectures face a bottleneck known as the \u2018memory wall\u2019 along with sharply rising power consumption. He then presented a \u2018memory-centric AI rack system\u2019 as the solution.<\/p>\n

\u201cThis system implements rack-level memory pooling and dynamic zero-copy data sharing by connecting CPUs and GPUs with next-generation CXL technology,\u201d he explained, \u201cand it is structured to significantly increase the speed of data movement in high-load workloads.\u201d He added, \u201cBy leveraging this, we can improve the KV cache reuse efficiency of collaborative agentic AI, accelerate the response speed of the multimodal omni model in personal agentic AI services, and solve the irregular memory access problems that arise in large-scale GNN* training.\u201d<\/p>\n

* <\/span>GNN (Graph Neural Network): An AI model that learns from graph-structured data connected by nodes and edges. It is used in fields where the relationships between data are important, such as social networks, molecular structures, and recommendation systems.<\/div>\n

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\u25b2 Vice President Youngpyo Joo, head of the System Architecture department, taking part in the panel discussion<\/p>\n

In addition, Vice President Youngpyo Joo, head of the System Architecture, took part in a panel discussion held on the afternoon of the third day. Conducted under the theme of \u201cIntegrating SW frameworks and APIs across companies for PIM\/PNM,\u201d the panel discussed the importance of the SW framework that connects customers and products within an ecosystem where multiple companies are intertwined in both competition and cooperation, and it also addressed the need for standardization in this area.<\/p>\n

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\u25b2 Team Leader Jongryool Kim of AI System Infra during his presentation<\/p><\/div><\/a>

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\u25b2 Technical Leader Younghoon Min of AI System Infra during his presentation<\/p><\/div><\/a>

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\u25b2 Technical Leader Juhee Lee of AI Platform SW during her presentation<\/p><\/div><\/a>

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In the \u2018Breakout\u2019 session held the same day, the engineers directly involved in development took the stage and gave detailed accounts of the need for key memory technologies, the background to their development, and the actual development journey and current status.<\/p>\n

First, Team Leader Jongryool Kim of AI System Infra spoke on \u201cAgentic AI Serving System with Computational Shared Memory Pool\u201d\u2014shared-memory-based technologies that enhance agentic AI service performance\u2014explaining that token sharing accelerates CPU-based tokenization, while KV cache sharing improves response speed and resource efficiency. He also highlighted the potential to further improve performance by offloading tokenization and real-time KV cache importance analysis to computational shared memory.<\/p>\n

Technical Leader Younghoon Min of AI System Infra, together with Professor Kiwan Maeng of Pennsylvania State University, spoke on \u201cA System Architecture using Computational Memory for Differentially Private Training\u201d\u2014a system architecture that uses computation-equipped memory to make AI training with differential privacy more efficient\u2014introducing a core technology that reduces the additional computational burden and data movement of the training process used to protect personal information, thereby improving training speed and energy efficiency.
\nFinally, Technical Leader Juhee Lee of AI Platform SW gave a presentation on \u201cStorage as a Performance Tier for LLM Serving.\u201d<\/p>\n

SK hynix said, \u201cAt this OCP Global Summit, it was especially meaningful that we could show how our next-generation memory solutions work in real systems,\u201d adding, \u201cWe will continue to pursue technological innovation so that AI technology can keep advancing with memory at its core.\u201d<\/p>\n

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