![\"Rulebreakers\u2019](\"https:\/\/d18r0a86za96sg.cloudfront.net\/wp-content\/uploads\/2026\/05\/27141302\/SK-hynix_Rulebreaker_1_MR-MUF_KV-banner_01-2.png\" "\\"Rulebreakers\u2019")
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The world runs on data\u2014a ceaseless tide of ones and zeros surging through networks, powering everything from streaming services to AI. To handle this data deluge, data centers must employ more advanced memory solutions that meet ever-growing performance demands.<\/p>\n
However, traditional methods of scaling memory are facing limitations. The constraints of processors and memory technologies, coupled with escalating costs and power consumption for data centers, have highlighted the need for a revolutionary approach. Enter Compute Express Link\u00ae<\/sup> (CXL\u00ae<\/sup>), a transformative memory interconnect technology designed to tackle the challenges of the AI era.<\/p>\n This Rulebreakers\u2019 Revolutions<\/span><\/a>\u202f episode will cover SK hynix\u2019s development of CXL solutions, detailing how the company overcame obstacles, such as a lack of industry specifications, to become a leader in the CXL field and a key contributor to the CXL ecosystem.<\/p>\n In the AI era, data centers need to continuously expand their memory capacity to handle ever-growing volumes of data. However, scaling memory capacity through traditional methods is becoming prohibitively expensive and inefficient. For example, adding terabyte (TB)-scale memory to a single CPU system can significantly increase the total cost of ownership* <\/sup> (TCO) and power consumption. Attempting to address this by increasing memory channels or integrating higher capacity memory often results in even greater power usage and heat generation, further inflating cooling system and management costs. This has underlined the need for innovative memory system designs which can process data faster, more efficiently, and cost effectively.<\/p>\n * <\/sup>Total cost of ownership: The complete cost of acquiring, operating, and maintaining an asset, including purchase, energy, and maintenance expenses.<\/p>\n \u25b2 Data center memory capacity needs to increase to handle the growing demands of the AI era<\/p>\n Over the past decade, the industry has been developing new memory interconnect technologies to meet this market demand. Memory interconnect technology refers to the method by which processors exchange data with memory, playing a critical role in determining the speed and efficiency of data processing. In traditional memory architectures, memory is physically connected to a nearby single processor, which can lead to an over-provision of memory resources when applications are not using the memory. New memory interconnect technologies such as CXL can overcome this issue by allowing multiple processors to share memory for improved efficiency.<\/p>\n This has led to great interest in CXL, however developing the technology would prove challenging as there was no precedent for the process and initially no industry-established specifications. Without the JEDEC* <\/sup> specifications which are generally provided for DRAM products, the development process for CXL was fundamentally more complex than usual.<\/p>\n * <\/sup>JEDEC Solid State Technology Association: With over 350 member companies, JEDEC is the global leader in developing open standards for the microelectronics industry.<\/p>\n Faced with having to develop new CXL products without industry specifications to break the barriers of memory scaling, SK hynix tapped into its internal expertise and collaborated with industry partners.<\/p>\n Following the introduction of CXL in 2019, SK hynix soon recognized the technology\u2019s capability to meet ever-growing memory scaling needs. As an open industry-standard interconnect, CXL unifies the interfaces of different system devices such as memory, storage, and processors. It supports features such as memory sharing, allowing multiple processors to access the same memory for improved data sharing, and memory pooling, in which memory from a common pool is assigned to processors for enhanced efficiency. Furthermore, CXL also enables memory switching, allowing hundreds of devices such as processors to share memory resources while independently processing data.<\/p>\n In addition to these innovative features, SK hynix became further convinced of CXL\u2019s immense potential after observing increased market and customer commitment to the technology and identifying its promise in addressing technical and cost challenges. However, the company had to begin the project by overcoming a significant obstacle\u2014a lack of industry specifications. SK hynix therefore soon set about developing its own basic requirement document after participating in CXL standardization activities and working with customers to define specifications. The company also collaborated with CXL controller companies to define controller requirements for the specifications document. Furthermore, the company has worked with JEDEC and the CXL Consortium* <\/sup> to enhance DRAM-related specifications for industry CXL standards.<\/p>\n * <\/sup>CXL Consortium: An open industry standards group that develops technical specifications for CXL.<\/p>\n \u25b2 SK hynix\u2019s CXL technology overcomes memory scaling challenges by expanding system capacity and bandwidth<\/p>\n Having helped set industry standards and develop relevant specifications, the company has accelerated its CXL development. For this process, SK hynix has identified key criteria to meet customer requirements\u2014cost efficiency, high capacity, optimized bandwidth, and reliability.<\/p>\n First, cost efficiency is paramount in CXL development. To counteract the high cost of CXL controllers, it is crucial to minimize the costs of memory media such as modules. As high capacity is essential to facilitate large-scale data processing, the company determined CXL memory should offer storage two to four times larger than existing DDR products. Furthermore, bandwidth design must be optimized to utilize the full performance potential of CXL modules. Finally, reliability and data integrity must match the high standards of the host memory to earn customer trust.<\/p>\n To meet these criteria, multiple departments across SK hynix are working on making terabyte-scale memory more affordable and efficient. This includes pioneering memory pooling technologies that enable resource sharing among multiple devices and developing NMP* <\/sup> technologies to handle data close to its source. These innovations are poised to deliver significant benefits to applications such as high-performance computing (HPC), in-memory databases, and AI.<\/p>\n * <\/sup>Near-memory processing (NMP): A technique that performs computations near data storage, reducing latency and boosting performance in high-bandwidth tasks like AI and HPC.<\/p>\n Through these efforts, SK hynix has been able to advance the development of groundbreaking CXL products which are set to revolutionize the memory field.<\/p>\n Since developing its first DDR5-based CXL sample in 2022<\/span><\/a>, SK hynix has been strengthening its CXL portfolio which includes the innovative CXL Memory Module-Double Data Rate 5 (CMM-DDR5). Leveraging high-speed PCIe Gen5 connections, CMM-DDR5 ensures smooth and rapid data processing. Available with up to 128 GB of storage, CMM-DDR5 also offers the high capacity required for the demands of today\u2019s AI and HPC applications. In addition, the module boasts high levels of power efficiency and security.<\/p>\n Real-world performance tests highlight the transformative impact of CMM-DDR5. The product can expand system bandwidth by up to 82% and capacity by up to 100% compared to systems equipped with only DDR5 DRAM. Tests also showed how AI workloads experienced a 31% increase in token per second performance and that HPC enjoyed a 33% improvement in throughput efficiency. As well as providing outstanding performance, CMM-DDR5 has aligned with both JEDEC and CXL Consortium standards. Currently, the verification and certification of CMM-DDR5 is being carried out by customers as the product moves closer to mass production.<\/p>\n \u25b2 SK hynix\u2019s CXL-based CMM-DDR5 enhances\u202fAI and HPC performance<\/p>\n SK hynix\u2019s other CXL solutions include Niagara 2.0, an integrated hardware and software solution that allows multiple hosts to efficiently share large memory pools to minimize unused or underutilized memory. Furthermore, CXL Memory Module-Ax (CMM-Ax), a high-performance memory module optimized for computational workloads, is notable for improving AI and data center efficiency.<\/p>\n Beyond hardware advancements, SK hynix has developed the Heterogeneous Memory Software Development Kit (HSMDK) to maximize the potential of its CXL memory. This software toolkit has even been integrated into Linux\u2019s operating system<\/span><\/a>, further enhancing its accessibility and usability. The development of both hardware and software solutions as well as its standardization efforts highlights how SK hynix is committed to creating a thriving CXL ecosystem.<\/p>\n In an interview with the SK hynix Newsroom, Distinguished Engineer* <\/sup> (DE) \u201cThomas\u201d Wonha Choi of Next-Gen Memory & Storage discussed the company\u2019s rulebreaking mentality for developing CXL technology. Responsible for standardization efforts with JEDEC and the CXL Consortium and pathfinding next-generation memory such as CXL, Choi spoke about CXL\u2019s development and its future impact.<\/p>\n * <\/sup>Distinguished Engineer: Senior SK hynix engineers who excel in their fields and are tasked with solving technical challenges and mentoring the next generation.<\/p>\n \u00a0<\/p>\n When did you and your team demonstrate outside-the-box thinking while developing industry-leading CXL technologies?<\/strong> * <\/sup>Voluntarily, Willingly, Brain, Engagement (VWBE): One of the employee values emphasized by SK Management System, or SKMS.<\/p>\n \u00a0<\/p>\n \u201cPersonally, I anticipated how the standardization and validation methods would merge DRAM and NAND approaches, and independently proposed and refined DRAM-related features within the CXL Consortium. Through these efforts, I am proud to have contributed to the company\u2019s initial CXL deployment strategy. It shows that, even when going into the unknown as we did for CXL, we harnessed our spirit of innovation and resilience to find answers to new problems.<\/p>\n \u201cAdditionally, I volunteered for demanding positions at JEDEC and the CXL Consortium, thereby contributing to elevating the company\u2019s stature in standardization efforts.\u201d<\/p>\n \u00a0<\/p>\n How do you see CXL evolving in the future AI ecosystem?<\/strong> \u201cBuilding such an ecosystem is not something SK hynix can achieve alone; it requires active collaboration with GPU and CPU manufacturers, CXL controller and switch vendors, and even CXL intellectual property (IP) companies. We plan to work with these organizations to further strengthen the CXL ecosystem.\u201d<\/p>\n<\/div>\n Read more articles from the Rulebreakers\u2019 Revolutions series<\/a><\/span><\/p>\n![\"[Rulebreakers\u2019](\"https:\/\/d18r0a86za96sg.cloudfront.net\/wp-content\/uploads\/2026\/05\/27141307\/SK-hynix_Rulebreaker_CXL_01.png\" "\\"[Rulebreakers\u2019")
<\/p>\n<\/div>\n\n\n<\/div>\nMission: Harnessing New Interconnect Tech for Memory Scaling<\/h3>\n
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<\/p>\n<\/div>\n\n\n<\/div>\nInto the Unknown: Developing Pioneering CXL Tech From Scratch<\/h3>\n
<\/div>\n<\/div>\n<\/div>\n![\"SK](\"https:\/\/d18r0a86za96sg.cloudfront.net\/wp-content\/uploads\/2026\/05\/27141316\/SK-hynix_Rulebreaker_CXL_03.png\" "\\"SK")
<\/p>\n<\/div>\n\n\n<\/div>\nSK hynix\u2019s Growing Product Lineup Driving the Future of CXL<\/h3>\n
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<\/p>\n<\/div>\n\n\n<\/div>\nRulebreaker Interview: \u201cThomas\u201d Wonha Choi, Next-Gen Memory & Storage<\/h3>\n
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\n\u201cDuring CXL development, we applied the working principles of SK hynix\u2019s VWBE* <\/sup> philosophy and tapped into experiences developing DRAM and NAND products to proactively propose working methods and initial CXL requirements to customers. Presenting these requirements in advance created more opportunities for technical deep dives into CXL, eventually leading to the successful development of our first CXL memory product.<\/p>\n![\"\u201cThomas\u201d](\"https:\/\/d18r0a86za96sg.cloudfront.net\/wp-content\/uploads\/2026\/05\/27141338\/SK-hynix_Rulebreaker_CXL_06.png\" "\\"\u201cThomas\u201d")
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\n\u201cCXL is expected to establish an ecosystem that enables the sharing of ultra-high-capacity memory. For CXL to expand further in the AI era, it will need to support computing nodes, secure cost-effective memory over 1 TB, provide bandwidth as and when it\u2019s needed, and maintain reliability and security at the memory level. This will help reduce TCO and improve memory utilization within system platforms.<\/p>\n
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