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\u201cDesign is not just what it looks and feels like.\u00a0Design is how it works.\u201d These words of Apple Co-Founder Steve Jobs emphasize the crucial role design plays in the functionality of products. This is particularly true in the semiconductor industry, where design involves defining the chip\u2019s architecture, purpose, and circuit layout to ultimately enable its smooth performance.<\/p>\n
The chip design scheme can also play a key role in overcoming challenges. When faced with scaling and data transmission limitations while developing HBM3E* <\/sup>, SK hynix introduced a pioneering 6-phase read-data-strobe (RDQS) design scheme. This world-first application enabled HBM3E to make huge strides in performance from its predecessor while maintaining the same packaging size.<\/p>\n This episode of Rulebreakers\u2019 Revolutions<\/span><\/a> reveals how SK hynix made the groundbreaking leap from the previous 4-phase to the 6-phase RDQS scheme, allowing the company to develop the world\u2019s best-performing HBM3E with enhanced capacity and increased reliability.<\/p>\n * <\/sup>HBM3E: The fifth-generation and latest High Bandwidth Memory (HBM) product. HBM is a high-value, high-performance product that revolutionizes data processing speeds by connecting multiple DRAM chips with through-silicon via (TSV).<\/p>\n \u00a0<\/p>\n While there are challenges when developing any semiconductor product, the development and manufacturing process for HBM solutions comes with its own set of specific issues. For example, there are difficulties when mass-producing HBM due to its use of through-silicon via (TSV) for chip stacking. When developing HBM3E, SK hynix found that TSV presented obstacles to its goal of maintaining the same packaging size as the previous generation HBM3 while increasing capacity.<\/p>\n Originally applied in SK hynix\u2019s first-generation HBM in 2013, TSV involves drilling microscopic holes in a DRAM chip to connect the electrodes that vertically penetrate the holes of the chip\u2019s upper and lower layers. Due to these holes, TSV signals occupy a significant amount of space in peripheral circuits* <\/sup>. As these circuits typically account for 20-30% of the total area in a memory product, the large number of TSV signals in HBM products hinders scaling efforts\u2014resulting in a need for TSV area optimization.<\/p>\n SK hynix also targeted advancing HBM3E\u2019s data transmission characteristics during development to ensure it could meet the heightened demands of the AI era. To meet this goal, the company focused on the CAS-to-CAS delay for reads (tCCDR) operation\u2014the minimum time delay required for memory to read data consecutively from cells in different ranks* <\/sup>. In particular, SK hynix aimed to secure an increased tCCDR margin. This margin allows for deviations in timing to ensure that data can be transmitted accurately, ultimately improving system reliability.<\/p>\n * <\/sup>Peripheral circuit: A logic circuit that is responsible for selecting and controlling the cells that store data. For HBM3E, the issue was that it becomes increasingly difficult to secure the minimum margin required for reliable data transmission during high-speed operation. This means that conflicts can occur when reading data across ranks at high speed, leading to potential read failures and a reduction in operational reliability.<\/p>\n Tasked with reducing the peripheral circuit size and improving the tCCDR margin, SK hynix turned its attention to developing a pioneering new design scheme which would open the door to the next-generation HBM3E.<\/p>\n \u00a0<\/p>\n <\/a><\/p>\n \u25b2 SK hynix overcame scaling and data transmission limitations in HBM3E by introducing the 6-phase RDQS scheme<\/p>\n Although SK hynix implemented several new design schemes and features in HBM3E, the world-first application of the 6-phase RDQS scheme was particularly notable. For HBM3, SK hynix had used the 4-phase RDQS scheme but the company saw an opportunity to push technical boundaries once again for HBM3E. This would ultimately enable the company to expand the memory capacity and improve the reliability of HBM3E.<\/p>\n Before looking at the advancements of the 6-phase RDQS scheme, it is prudent to consider the scheme\u2019s role in HBM. The RDQS scheme is a circuit that produces the RDQS signals required for transmitting data from the HBM\u2019s core dies, which contain the cells, to the base die, which contains the peripheral circuit. Overall, the RDQS scheme aims to minimize data skew* <\/sup> from different ranks to avoid read failures.<\/p>\n * <\/sup>Data skew: The uneven distribution of data across different partitions in large-scale data processing. This can result in longer processing times as some partitions are required to handle more data than others.<\/p>\n \u25b2 Schematic diagrams showing the structural differences between the 4-phase and 6-phase RDQS schemes (upper diagrams) and a comparison of the schemes\u2019 tCCDR margin (lower diagrams) (Source: Jinhyung Lee et al., High-Density Memories and High-Speed Interfaces<\/em><\/span><\/a>, ISSCC 2024)<\/p>\n So how did the introduction of the 6-phase RDQS scheme reduce the size of the peripheral circuit? In the 4-phase RDQS scheme, multiple sets of FIFO-out data strobes* <\/sup> (FDQS) and RDQS TSVs are required which inevitably leads to an increase of the peripheral area. The introduction of the 6-phase RDQS scheme can reduce the area of the peripheral circuit by cutting the number of FDQS and RDQS TSVs in half. This reduction of TSV signals means that the number of signals going back and forth between ranks is reduced, which can reduce the peripheral height.<\/p>\n * <\/sup>FIFO:\u00a0A data structure that holds elements in the order they are received and provides access to those elements using a first-in, first-out basis.<\/p>\n Furthermore, the 6-phase RDQS scheme improved the tCCDR margin during the high-speed operation of HBM3E. This was realized as there is enough space between signals in the new scheme, so there is more margin for data transmission across ranks, or tCCDR operation. By securing this larger margin, the system becomes more tolerant of any deviations in timing, reducing the likelihood of read failures and therefore increasing system reliability.<\/p>\n \u00a0<\/p>\n \u25b2 The application of the 6-phase RDQS scheme enabled HBM3E to maintain the same packaging size as HBM3 while offering improved density<\/p>\n \u00a0<\/strong> In addition, the increased tCCDR margin stabilized the data transmission characteristics, which contributed to the enhancement in HBM3E\u2019s data processing speed compared to its predecessor. While the 8-layer HBM3 can process up to 819 GB of data per second, the 8-layer HBM3E offers industry-leading data processing speeds of 1.18 terabytes (TB) per second. This rapid processing speed coupled with its vast capacity ensures HBM3E is optimized to meet the requirements of today\u2019s AI applications.<\/p>\n \u00a0<\/p>\n To find out more about the rulebreaking approach which led to the application of the 6-phase RDQS scheme to HBM3E, the SK hynix newsroom interviewed Technical Leader (TL) Youngjun Ku of Leading HBM Design. Ku discussed the significance of the new design scheme, as well as the challenges faced during the application process.<\/p>\n Why is the 6-phase RDQS scheme significant for HBM?<\/strong> \u201cWe believe that collaboration with our customers and the foundry industry will become even more important in the future as HBM products advance with the development of HBM4 and HBM4E, which double the data bandwidth and customized requirements. To maintain our leadership, we need to design products appropriate to our customers\u2019 needs.\u201d<\/p>\n How did your team\u2019s rulebreaking approach ensure the development of the 6-phase RDQS scheme?<\/strong> Read more articles from the Rulebreakers\u2019 Revolutions series<\/a><\/span><\/p>\n![\"[Rulebreakers\u2019](\"https:\/\/d18r0a86za96sg.cloudfront.net\/wp-content\/uploads\/2026\/05\/27144112\/SK-hynix_Rulebreakers-Revolutions-3-HBM3E-Design_01.png\" "\\"[Rulebreakers\u2019")
<\/p>\n\n\n<\/div>\nOvercoming Scaling & Data Transmission Limitations in HBM3E<\/h3>\n
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\n* <\/sup>Rank: A collection of basic data transmission units sent to the CPU from the DRAM module. A rank typically refers to 64 bytes of data to be transferred to the CPU as a bundle.<\/p>\n\n\n<\/div>\nA New Design: Leaping Forward With the World\u2019s First 6-Phase RDQS Scheme<\/h3>\n
<\/div>\n<\/div>\n<\/div>\n![\"SK](\"https:\/\/d18r0a86za96sg.cloudfront.net\/wp-content\/uploads\/2026\/05\/27144117\/SK-hynix_Rulebreakers-Revolutions-3-HBM3E-Design_02.png\" "\\"SK")
<\/p>\n![\"Schematic](\"https:\/\/d18r0a86za96sg.cloudfront.net\/wp-content\/uploads\/2026\/05\/27144122\/SK-hynix_Rulebreakers-Revolutions-3-HBM3E-Design_03.png\" "\\"Schematic")
<\/p>\n\n\n<\/div>\nPower in a Small Package: 6-phase RDQS Scheme Unlocks HBM3E<\/h3>\n
<\/div>\n<\/div>\n<\/div>\n![\"The](\"https:\/\/d18r0a86za96sg.cloudfront.net\/wp-content\/uploads\/2026\/05\/27144128\/SK-hynix_Rulebreakers-Revolutions-3-HBM3E-Design_04.png\" "\\"The")
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\nThe application of the 6-phase RDQS scheme contributed to the significant advancements in HBM3E\u2019s key characteristics. First, the scheme enabled the reduction of the peripheral circuit height in the base die by 31%. Crucially, this reduction in the peripheral circuit height helped ensure that HBM3E has the same packaging size as HBM3 while offering an increased capacity from 16 Gb to 24 Gb.<\/p>\n\n\n<\/div>\nRulebreaker Interview: Youngjun Ku, Leading HBM Design<\/h3>\n
<\/div>\n<\/div>\n<\/div>\n![\"Technical](\"https:\/\/d18r0a86za96sg.cloudfront.net\/wp-content\/uploads\/2026\/05\/27144134\/SK-hynix_Rulebreakers-Revolutions-3-HBM3E-Design_05.png\" "\\"Technical")
<\/p>\n<\/div>\nWhat were the main challenges when applying the 6-phase RDQS scheme to HBM3E?<\/strong>
\n\u201cThe 6-phase RDQS scheme significantly increases the overall design difficulty due to its complexity.\u201cThe most straightforward way to address the issues with HBM3E was to improve transistor performance. However, when it seemed to reach certain limits with no room for further improvement, we resolved this by turning our attention to the design scheme, which was particularly challenging when working with HBM.\u201cAs HBM products have a short gap between generations while realizing huge leaps in performance, the circuits require multiple changes. However, we tackled any problems through collaboration with numerous departments within the DRAM Design division.\u201d<\/p>\n<\/div>\n![\"Technical](\"https:\/\/d18r0a86za96sg.cloudfront.net\/wp-content\/uploads\/2026\/05\/27144145\/SK-hynix_Rulebreakers-Revolutions-3-HBM3E-Design_06.png\" "\\"Technical")
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\n\u201cTo meet the demands of the AI era, HBM products need to increase their data processing speed. This requires stable data transmission by securing HBM\u2019s timing margin. Therefore, schemes such as 6-phase RDQS, which help secure data transmission characteristics through TSV between the base and core die, will be essential in the age of AI.<\/p>\n
\n\u201cWhen designing HBM products, there are a lot of challenges. The members of Leading HBM Design were constantly brainstorming to find solutions to these problems. Rather than fearing changes to the circuit design, we achieved great results by trusting in our ability to overcome challenges.\u201d<\/p>\n<\/div>\n
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