{"id":1799,"date":"2024-09-26T06:00:38","date_gmt":"2024-09-26T06:00:38","guid":{"rendered":"http:\/\/localhost:8080\/sk-hynix-spotlights-ai-memory-solutions-industry-collaboration-at-tsmc-oip-ecosystem-forum-2024\/"},"modified":"2026-07-29T14:55:05","modified_gmt":"2026-07-29T05:55:05","slug":"sk-hynix-spotlights-ai-memory-solutions-industry-collaboration-at-tsmc-oip-ecosystem-forum-2024","status":"publish","type":"post","link":"https:\/\/news.skhynix.com\/en\/sk-hynix-spotlights-ai-memory-solutions-industry-collaboration-at-tsmc-oip-ecosystem-forum-2024\/","title":{"rendered":"SK hynix Spotlights AI Memory Solutions & Industry Collaboration at TSMC OIP Ecosystem Forum 2024"},"content":{"rendered":"

SK hynix showcased its advanced AI memory and data center products at the TSMC Open Innovation Platform (OIP) Ecosystem Forum 2024 held on September 25 in San Jose, California. The annual event brings together TSMC OIP* <\/sup> members and the semiconductor design community to foster industry collaboration and drive innovation. At this year\u2019s event, SK hynix strengthened its strategic partnership with the host TSMC<\/a><\/span> based on HBM* <\/sup> development and presented key products, including its HBM3E and the world\u2019s first 1cnm DDR5 product.<\/p>\n

* <\/sup>Open Innovation Platform (OIP): A comprehensive design technology infrastructure encompassing all areas of integrated circuit implementation which aims to promote innovation. Members include a variety of semiconductor design and manufacturing companies.
\n* <\/sup>High Bandwidth Memory (HBM): A high-value, high-performance product that revolutionizes data processing speeds by connecting multiple DRAM chips with through-silicon via (TSV).<\/p>\n

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\u25b2 SK hynix\u2019s booth at the TSMC OIP Ecosystem Forum 2024<\/p>\n

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Innovation in Focus: Leading HBM, AI & Data Center Products at the Booth<\/h3>\n
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Situated next to the main TSMC booth, the SK hynix booth featured two main sections which showcased the company\u2019s global No. 1 HBM and AI\/data center solutions, respectively.<\/p>\n

The HBM section featured the company\u2019s industry-leading HBM3E. Boasting rapid processing speeds, high capacity, and outstanding heat dissipation, HBM3E is optimized for AI applications. This section not only highlighted the technological achievements of SK hynix, but also illustrated the strategic importance of its collaboration with TSMC to push the boundaries of AI innovation. Moreover, SK hynix\u2019s HBM leadership was further underlined by the company\u2019s recent announcement that it had become the first in the industry to begin volume production of the 12-layer HBM3E.<\/a><\/span><\/p>\n

In the AI and data center solutions section, SK hynix presented the industry\u2019s first 16Gb DDR5 product<\/a><\/span> built using the 1c node, the sixth generation of the 10 nm process. Compared to the previous generation, the new product offers 11% faster operating speeds of 8 gigabits per second\u00a0(Gbps) and 9% greater power efficiency to help data centers cut electricity costs. Marking a significant advancement in DRAM scaling, the 1cnm technology is set to be applied to other SK hynix products in the future.<\/p>\n

This section also featured other key products in SK hynix\u2019s portfolio, including DDR5 MCR DIMM* <\/sup>, DDR5 3DS RDIMM* <\/sup>, LPCAMM2* <\/sup>, GDDR7* <\/sup>, and LPDDR5T* <\/sup>. Each solution reflects significant advancements in AI memory technology, catering to diverse needs from high-performance computing (HPC) to mobile and graphics-intensive applications.<\/p>\n

* <\/sup>Multiplexer Combined Ranks Dual In-line Memory Module (MCR DIMM): A module product with multiple DRAMs bonded to a motherboard in which two ranks\u2014basic information processing units\u2014operate simultaneously, resulting in improved speed.
\n* <\/sup>3D Stacked Memory Registered Dual In-line Memory Module (3DS RDIMM): A high-density memory module used in servers and other applications to vertically connect DRAM dies through TSV, reducing module package height and boosting data transfer speeds.
\n* <\/sup>Low Power Compression Attached Memory Module 2 (LPCAMM2): LPDDR5X-based module solution that offers power efficiency and high performance as well as space savings. It offers performance levels equivalent to two DDR5 SODIMMs, making it optimized for on-device AI.
\n* <\/sup>Graphics DDR (GDDR): A standard specification of graphics DRAM defined by the Joint Electron Device Engineering Council (JEDEC) and specialized for processing graphics more quickly. It is now one of the most popular memory chips for AI and big data applications.
\n* <\/sup>Low Power Double Data Rate 5 Turbo (LPDDR5T): Low-power DRAM for mobile devices, including smartphones and tablets, aimed at minimizing power consumption and featuring low voltage operation. LPDDR5T is an upgraded product of the 7th generation LPDDR5X and will be succeeded by the 8th generation LPDDR6.<\/p>\n

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\u25b2 Other products on display included DDR5 MCR DIMM, DDR5 3DS RDIMM, LPCAMM2, LPDDR5T, and GDDR7<\/p>\n

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Presentation on 2.5D SiP Study for Enhancing HBM Quality & Reliability<\/h3>\n
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During the forum, SK hynix\u2019s Byoungdo Lee, Technical Leader of HBM PKG TE, gave a talk titled \u201cA Collaborative Study on 2.5D System-in-Packages for Better Quality and Reliability of HBM<\/a><\/span>.\u201d Having encountered limitations using a proxy package to accurately recreate SiP* <\/sup> conditions for the study, SK hynix opted to conduct open collaboration with companies including TSMC. This collaboration included preliminary evaluations as well as thermal and mechanical simulations at the SiP level. The study found that HBM products with SK hynix\u2019s MR-MUF* <\/sup> technology offer greater quality and reliability, and are ultimately able to overcome stacking limitations.<\/p>\n

Additionally, the presentation covered three main advancements for HBM4, the upcoming sixth generation of HBM. Lee addressed the use of base logic die wafers* <\/sup> to improve performance and power efficiency, as well as the development of 16-layer HBM utilizing Advanced MR-MUF or hybrid bonding* <\/sup> packaging technology to meet demand for higher density products. Lastly, Lee spoke about planned SiP-level verification developments which aim to mitigate risks associated with the increased total product thickness.<\/p>\n

* <\/sup>System-in-Package (SiP): A method of stacking and connecting multiple semiconductor chips in a single package to improve performance and efficiency, enabling advanced functions like high-speed data processing.
\n* <\/sup>Mass reflow-molded underfill (MR-MUF): A technology that ensures secure and reliable connections in densely stacked chip assemblies by melting the bumps between stacked chips.
\n* <\/sup>Base logic die wafer: A foundational semiconductor layer that contains the memory controller and logic circuitry, enabling high-speed communication between the stacked memory dies and the system.
\n* <\/sup>Hybrid bonding: A technology that stacks two or more chips atop one another in the same package, enabling high-density interconnections crucial for advanced HBM products.<\/p>\n

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\u25b2 SK hynix\u2019s Byoungdo Lee presenting an OIP Partner Technical Talk on enhancing HBM<\/p>\n

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Strengthening AI Memory Leadership & Strategic Partnerships<\/h3>\n
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At the TSMC OIP Ecosystem Forum 2024, SK hynix underlined its AI memory leadership and strengthened key industry partnerships. By showcasing key products such as the industry-leading HBM3E and the world\u2019s first 1cnm DDR5 product, the company emphasized its ability to break technological boundaries. Looking ahead, the company is set to continue advancing its portfolio through collaboration with global partners to meet the growing needs of the AI era.<\/p>\n

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SK hynix showcased its advanced AI memory and data center products at the TSMC Open Innovation Platform (OIP) Ecosystem Forum 2024 held on September 25 in San Jose, California. The annual event brings together TSMC OIP1 members and the semiconductor design community to foster industry collaboration and drive innovation. At this year\u2019s event, SK hynix [\u2026]<\/p>\n","protected":false},"author":23,"featured_media":1793,"comment_status":"closed","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"_migrated_source_id":15869,"footnotes":"","_members_access_role":[],"_members_access_error":""},"categories":[5],"tags":[1311,37],"class_list":["post-1799","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-tech-and-ai","tag-oip","tag-tsmc"],"acf":[],"_links":{"self":[{"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/posts\/1799","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/users\/23"}],"replies":[{"embeddable":true,"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/comments?post=1799"}],"version-history":[{"count":4,"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/posts\/1799\/revisions"}],"predecessor-version":[{"id":11666,"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/posts\/1799\/revisions\/11666"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/media\/1793"}],"wp:attachment":[{"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/media?parent=1799"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/categories?post=1799"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/tags?post=1799"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}