{"id":2356,"date":"2023-10-31T00:00:32","date_gmt":"2023-10-31T00:00:32","guid":{"rendered":"http:\/\/localhost:8080\/3d-fe-nand-to-surpass-3d-ctn-memory\/"},"modified":"2026-07-29T14:56:25","modified_gmt":"2026-07-29T05:56:25","slug":"3d-fe-nand-to-surpass-3d-ctn-memory","status":"publish","type":"post","link":"https:\/\/news.skhynix.com\/en\/3d-fe-nand-to-surpass-3d-ctn-memory\/","title":{"rendered":"3D Fe-NAND to Surpass 3D CTN Memory Following Cell Stacking Breakthrough"},"content":{"rendered":"

Conventional 3D NAND memory stores data by trapping charges in the silicon nitride film known as a charge trade nitride (CTN) layer. Despite its widespread use, 3D CTN NAND faces limitations in achieving memory expansion through cell stacking due to cell-to-cell interference and spacer\u00a0oxide thickness between vertically adjacent cells. This has prompted the industry to search for alternatives to 3D CTN NAND technology that overcome these limitations, with 3D ferroelectric*<\/span> NAND (Fe-NAND) emerging as a potential successor.<\/p>\n

In 2022, researchers at SK hynix\u2019s Revolutionary Technology Center (RTC) revealed they had demonstrated 3D Fe-NAND triple-level-cell*<\/span> (TLC) operation<\/span><\/a> using the ferroelectric HfO2<\/sub>*<\/span>. This article will focus on the RTC\u2019s latest research presented at the 2023 Very Large-Scale Integration (VLSI) Symposium, which showed 3D Fe-NAND quad-level cell*<\/span> (QLC) operation for the first time using the 3D CTN NAND test vehicle*<\/span>.<\/p>\n

*<\/span>Ferroelectric (FE): A material which exhibits spontaneous\u202felectric polarization without an external electrical field\u202fthat can be reversed in direction by the application of an appropriate\u202felectric field.
\n*<\/span>Triple-level cell (TLC): A form of NAND flash memory that can store up to 3 bits of data per memory cell.
\n*<\/span>Hafnium Oxide (HfO2): A mature high-k dielectric applied to semiconductor materials due to its high dielectric constant, thermodynamic stability, and the simplicity with which it can be deposited.
\n*<\/span>Quad-level cell (QLC): A form of NAND flash memory that can store up to 4 bits of data per memory cell.
\n*<\/span>Test vehicle: A circuit or IC designed for the purpose of evaluating one or many device characteristics.<\/p>\n

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Finding the Ideal Cell Structure to Increase the PE Window<\/h3>\n
<\/div>\n<\/div>\n<\/div>\n

For 3D Fe-NAND to realize TLC and QLC operation, it required further expansion of the program\/erase (PE) window*<\/span>. The latest RTC research proposed novel 3D Fe-NAND cell structures that can enlarge the PE window up to 10.54 V through cell stack optimization, thereby demonstrating the feasibility of QLC operation.<\/p>\n

*<\/span>Program\/erase window (PE window): The process window of erasing and writing a cell. The more P\/E cycles that the NAND technology can sustain, the better the endurance of the device.<\/p>\n

\"Table<\/p>\n

Figure 1. Table showing key characteristics of four cell stack structures (S1\u2013S4)<\/p>\n

\"Graphs<\/p>\n

Figure 2. Graphs comparing the (a) erase and (b) program performances of S1\u2013S4<\/p>\n

Figure 1 summarizes the four types of cell structures (S1\u2013S4) evaluated in this study and compares the electrical characteristics including the standard PE window, the post 3k cycle PE window, and the channel to gate leakage current. Figure 2(a) and (b) show the transfer characteristics of the four cell structures as the researchers erased and programmed the cells using the conventional ISPE*<\/span> and ISPP*<\/span> methods. In particular, S4 achieved the enlarged P\/E window of 10.54 V by reducing the leakage current and optimizing the cell structures of the ferroelectric stack and the top interlayer.<\/p>\n

*<\/span>Incremental Step Pulse Erase (ISPE): A memory programming method in which a memory element\u00a0is programmed to a specific state or set to an erase state using small, incremental voltage steps or pulses.
\n*<\/span>Incremental Step Pulse Programming (ISPP): A memory programming method in which a series of programming pulses of increasing magnitude are applied to select memory cells to gradually raise their threshold voltage.<\/p>\n

\"Line<\/p>\n

\u25b2 Figure 3. Line graphs for S4 showing its (a) TLC threshold voltage (Vth) distribution (b) QLC Vth distribution and\u00a0(c) post 3k cycle Vth distribution<\/p>\n

Both TLC and QLC operations were performed on S4. Figure 3(a) shows TLC verification results for S4 with the minimum gap margin of 0.45 V between two adjacent threshold voltage (Vth<\/sub>) states. This represents a significant improvement from the RTC\u2019s previous data, which showed a minimum gap margin of 0.11 V. Moreover, with the expanded PE window, Figure 3(b) shows S4\u2019s QLC operation is demonstrated with the minimum gap margin of 0.24 V. In Figure 3(c), QLC Vth distribution after 3k cycling stress is shown with the reduced minimum gap margin of 0.14V. The QLC operation after the 3k cycle is verified not only by expanding the PE window, but also by improving endurance properties as a result of cell stack engineering.<\/p>\n

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3D Fe-NAND Opens the Door to a New Era<\/h3>\n
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To overcome the limitations of conventional 3D CTN NAND, the researchers successfully fabricated the HfO2<\/sub>-based 3D Fe-NAND. The new NAND research shows that optimizing the cell stack leads to an expansion of the PE window, while the QLC operation was also demonstrated which suggests that 3D Fe-NAND is a promising potential solution in the post-3D NAND era.<\/p>\n

For more information regarding RTC\u2019s research, please visit the center\u2019s <\/em>research website (<\/em>https:\/\/research.skhynix.com<\/em><\/a><\/span>). The RTC operates the site to<\/em> share insights on its ongoing research of future technologies and to actively communicate with various global research organizations.<\/em><\/p>\n

\"\"<\/p>\n","protected":false},"excerpt":{"rendered":"

Conventional 3D NAND memory stores data by trapping charges in the silicon nitride film known as a charge trade nitride (CTN) layer. Despite its widespread use, 3D CTN NAND faces limitations in achieving memory expansion through cell stacking due to<\/p>\n","protected":false},"author":7,"featured_media":2351,"comment_status":"closed","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"_migrated_source_id":13173,"footnotes":"","_members_access_role":[],"_members_access_error":""},"categories":[5],"tags":[667,668,92,600,473],"class_list":["post-2356","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-tech-and-ai","tag-3d-ctn-memory","tag-3d-fe-nand","tag-qlc","tag-revolutionary-technology-center","tag-rtc"],"acf":[],"_links":{"self":[{"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/posts\/2356","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/users\/7"}],"replies":[{"embeddable":true,"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/comments?post=2356"}],"version-history":[{"count":4,"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/posts\/2356\/revisions"}],"predecessor-version":[{"id":11727,"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/posts\/2356\/revisions\/11727"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/media\/2351"}],"wp:attachment":[{"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/media?parent=2356"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/categories?post=2356"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/tags?post=2356"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}