{"id":2690,"date":"2023-05-19T06:00:52","date_gmt":"2023-05-19T06:00:52","guid":{"rendered":"http:\/\/localhost:8080\/meet-the-sk-hynix-team-behind-the-worlds-first-12-layer-hbm3\/"},"modified":"2026-06-10T11:36:24","modified_gmt":"2026-06-10T11:36:24","slug":"meet-the-sk-hynix-team-behind-the-worlds-first-12-layer-hbm3","status":"publish","type":"post","link":"https:\/\/news.skhynix.com\/en\/meet-the-sk-hynix-team-behind-the-worlds-first-12-layer-hbm3\/","title":{"rendered":"Strengthening HBM Market Leadership: Meet the SK hynix Team Behind the World\u2019s First 12-Layer HBM3"},"content":{"rendered":"

\u201cAI models continue to grow and drive demand for large memory capacity. We welcome the efforts by SK hynix to increase HBM memory capacity to support cutting-edge AI models.\u201d<\/strong><\/em>
\n\u2013 Roman Kyrychynskyi, CVP, Product Management, AMD<\/p>\n

The recent boom in demand for artificial intelligence (AI) services such as big data and ChatGPT has intensified competition for the next-generation semiconductor products that support such technologies. SK hynix is pushing technological limits to lead the development of these high-performance products, such as its High Bandwidth Memory (HBM)*<\/span> solutions.<\/p>\n

*<\/span>High Bandwidth Memory (HBM): A high-value and high-performance product that revolutionizes data processing speed by vertically connecting multiple DRAM chips using Through Silicon Via (TSV). HBM3 is the fourth and latest generation of the series.<\/p>\n

After developing the world\u2019s first HBM3 in 2021 and successfully mass producing it the following year, SK hynix announced in April 2023 that it had developed the world\u2019s first 12-layer HBM3<\/a><\/span> and provided samples to customers including AMD. The latest product offers an industry-leading 24 GB memory capacity in the same size package as its predecessor, highlighting the company\u2019s technical leadership in the field.<\/p>\n

To find out more about the 12-layer HBM3, the SK hynix Newsroom met with members of the team behind the product. The team explained about the product\u2019s features, the application of cutting-edge technologies including advanced MR-MUF*<\/span>, the story behind its development, and their ambitions for the next generation of solutions.<\/p>\n

*Mass Reflow-Molded Underfill (MR-MUF): A process in which semiconductor chips are stacked and a liquid protective material is injected into the space between the chips and then hardened to protect the chips and the surrounding circuitry. Compared to applying a film-type material after each chip is stacked, MR-MUF is a more efficient process and offers effective heat dissipation.<\/p>\n

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\u25b2 The 12-layer HBM3 offers the largest industry memory capacity of 24 GB<\/p>\n

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Achieving the Highest Capacity HBM3 With Advanced MR-MUF<\/h3>\n
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The 12-layer HBM3 offers 50% more memory capacity than its 16 GB predecessor by increasing the number of DRAM chips from 8 to 12. This enabled SK hynix to achieve the largest industry memory capacity of 24 GB while also maintaining the same height, or thickness, as the 16 GB product. In other words, SK hynix was able to develop a solution that can process more data in the same space as before. So how did the company achieve such a feat?<\/p>\n

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\u25b2 An overview of the technologies used to develop the 12-layer HBM3<\/p>\n

In order to increase the product\u2019s capacity, or number of layers, while maintaining its thickness, the stacked DRAM chips had to be 40% thinner than before. However, this can cause problems such as the chips bending easily. The team overcame these technical issues by applying an improved epoxy molding compound (EMC)*<\/span> and utilizing advanced MR-MUF technology with a new stacking method.<\/p>\n

*<\/span>Epoxy molding compound (EMC): A heat dissipation material based on epoxy resin, a type of thermosetting polymer, that seals semiconductor chips to protect them from environmental factors such as heat, moisture, and shock.<\/p>\n

SK hynix is currently providing samples of the new solution to a number of its global customers for performance testing and has received an overwhelmingly positive response.<\/p>\n

\u201cAI models continue to grow and drive demand for large memory capacity. We welcome the efforts by SK hynix to increase HBM memory capacity to support cutting-edge AI models,\u201d said Roman Kyrychynskyi, corporate vice president (CVP) of Product Management at AMD.<\/p>\n

\u201cWith the 12-layer HBM3, System-on-Chip (SoC)*<\/span> companies can achieve a 1.5-times memory capacity increase with the same size product without the need for additional space in the system,\u201d said PL Wang-su Kim, who is in charge of DRAM product planning at SK hynix. \u201cMany customers have shown high confidence in our technology. We will start supplying the new product in the second half of 2023.\u201d<\/p>\n

*<\/span>System-on-Chip (SoC): A product that integrates multimedia components (graphics, audio, and video), semiconductors (CPU and DRAM), and all hardware components necessary for a computer to process instructions into one chip.<\/p>\n

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Securing Excellent Heat Dissipation, Productivity, and Reliability<\/h3>\n
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\u25b2 Wang-su Kim explains the development of the 12-layer HBM3<\/p>\n

\u201cSK hynix anticipated customer and market needs and had already put a 24 GB product on the development roadmap in 2022,\u201d said Kim. \u201cThis allowed us to move quickly to develop the technology and introduce the 12-layer HBM3 24 GB package.\u201d<\/p>\n

Kim added that the 12-layer HBM3 was developed in about ten months following the mass production of the previous 8-layer version. During this remarkably rapid product development process, the team inevitably encountered some challenges. In particular, stacking 12 DRAM chips, which are 40% thinner, with a 13% narrower gap than before made it difficult to maintain control of the chips and apply the original packaging process. PL Jong-oh Kwon, in charge of wafer-level package (WLP) back-end (BE) development, revealed that the solution was to introduce the advanced MR-MUF process.<\/p>\n

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\u25b2 Jong-oh Kwon (standing) explains the advanced MR-MUF technology<\/p>\n

\u201cThe advanced MR-MUF process offers three improvements over the original MR-MUF,\u201d said Kwon. \u201cFirst, we incorporated new technology to control the thinning of the wafers so they don\u2019t bend. Next, during the 12-layer stacking process, we momentarily applied intense heat to ensure that the bumps connecting the chips were evenly spliced. Finally, we placed a new heat-dissipating EMC material under a vacuum and applied 70 tons of pressure to fill the tight spaces between the chips.\u201d<\/p>\n

Kwon emphasized that advanced MR-MUF retains the advantages of the original MR-MUF, while increasing productivity approximately three-fold and boosting heat dissipation by around 2.5 times.<\/p>\n

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Cross-Organizational Collaboration and Testing Key to Success<\/h3>\n
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PL Kim credited cross-organizational collaboration as a major factor in the product\u2019s success. He highlighted how this \u201cone-team\u201d mindset enabled harmonized product development. This is shown by the combination of the device technology that prevents defects during the stacking process, the design technology that ensures uniform cell speed in higher layers, and the package technology that supports effective heat dissipation.<\/p>\n

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\u25b2 Jin-woo Park (left) and Ju-heon Yang (right) talk about the development process of the 12-layer HBM3<\/p>\n

A sharp focus on testing to ensure quality and reliability was also a key success factor. \u201cThere are hundreds of thousands of bumps between chips,\u201d said PL Ju-heon Yang, who is responsible for WLP front-end (FE) development. \u201cWe tested them one by one to find the optimal bonding conditions and minimize defects.\u201d<\/p>\n

\u201cWith 1.5 times more chips stacked than before, it was difficult to secure yield and quality early on,\u201d said PL Hyung-su Sung, who tests DRAM wafers and HBM3 on the HBM Product Engineering (PE) team. \u201cAfter numerous attempts, we established an optimal test baseline for the 12-layer solution.\u201d<\/p>\n

As with other solutions, the 12-layer HBM3 can only be considered a finished product when it is packaged for the customer without defects. PL Kim and PL Jin-woo Park, who is in charge of HBM package products, are working hard to complete this process and are currently carrying out customer performance verification.<\/p>\n

\u201cWe are actively communicating with our customers to solve any issues,\u201d said Park. \u201cWe are building a win-win \u2018HBM ecosystem\u2019 so that we can have a mutual understanding with our customers, share information, and create the best products.\u201d<\/p>\n

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Continuing to Lead the Way With HBM3E & HBM4<\/h3>\n
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\u25b2 Hyung-su Sung (left), Wang-su Kim (center), and Jong-oh Kwon (right) share their thoughts on the development of the 12-layer HBM3<\/p>\n

Although there is still a long way to go, the team members are overjoyed with their achievements. \u201cThere is always a sense of trepidation to go down an unknown road, but it makes the joy of reaching your goal even greater,\u201d said Sung. \u201cWe are proud to have developed the world\u2019s first 12-layer HBM3.\u201d<\/p>\n

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\u25b2 Wang-su Kim analyzes the 12-layer HBM3<\/p>\n

The team is committed to maintaining SK hynix\u2019s leadership in the HBM field by continuing to advance HBM solutions in the future. With plans to develop the next-generation HBM3E and HBM4 products, the company will further enhance its reputation as a pioneer of HBM technology unmatched by its rivals.<\/p>\n","protected":false},"excerpt":{"rendered":"

\u201cAI models continue to grow and drive demand for large memory capacity. We welcome the efforts by SK hynix to increase HBM memory capacity to support cutting-edge AI models.\u201d \u2013 Roman Kyrychynskyi, CVP, Product Management, AMD The recent boom in<\/p>\n","protected":false},"author":23,"featured_media":2682,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"_migrated_source_id":11682,"footnotes":"","_members_access_role":[],"_members_access_error":""},"categories":[5],"tags":[295,760,13,294,17],"class_list":["post-2690","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-tech-and-ai","tag-12-layer","tag-emc","tag-hbm","tag-hbm3","tag-mr-muf"],"acf":[],"_links":{"self":[{"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/posts\/2690","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/users\/23"}],"replies":[{"embeddable":true,"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/comments?post=2690"}],"version-history":[{"count":3,"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/posts\/2690\/revisions"}],"predecessor-version":[{"id":6981,"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/posts\/2690\/revisions\/6981"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/media\/2682"}],"wp:attachment":[{"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/media?parent=2690"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/categories?post=2690"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/tags?post=2690"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}