{"id":3177,"date":"2022-08-01T00:00:17","date_gmt":"2022-08-01T00:00:17","guid":{"rendered":"http:\/\/localhost:8080\/sk-hynix-develops-ddr5-dram-cxltm-memory-to-expand-the-cxl-memory-ecosystem\/"},"modified":"2026-06-17T01:47:04","modified_gmt":"2026-06-17T01:47:04","slug":"sk-hynix-develops-ddr5-dram-cxltm-memory-to-expand-the-cxl-memory-ecosystem","status":"publish","type":"post","link":"https:\/\/news.skhynix.com\/en\/sk-hynix-develops-ddr5-dram-cxltm-memory-to-expand-the-cxl-memory-ecosystem\/","title":{"rendered":"SK hynix Develops DDR5 DRAM CXLTM Memory  to Expand the CXL Memory Ecosystem"},"content":{"rendered":"<div class=\"post-intro\"><strong>\u00b7 SK hynix develops its first DDR5 DRAM-based CXL sample<\/strong><br \/>\n<strong>\u00b7 Expandable CXL memory to secure the technology accessibility by development of dedicated HMSDK<\/strong><br \/>\n<strong>\u00b7 SK hynix to expand the CXL memory ecosystem while strengthening its presence in the next-gen memory solutions market<\/strong><\/div>\n<p><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-9576\" src=\"https:\/\/d18r0a86za96sg.cloudfront.net\/wp-content\/uploads\/2026\/05\/27174710\/SK-hynix_CXL_v02_01.png\" alt=\"\" width=\"1000\" height=\"600\" \/><\/p>\n<p>SK hynix Inc. (or \u201cthe company\u201d, <a href=\"http:\/\/www.skhynix.com\" target=\"_blank\" rel=\"noopener noreferrer\"><span style=\"text-decoration: underline;\">www.skhynix.com<\/span><\/a>) has developed its first DDR5 DRAM-based CXL (Compute Express Link) memory samples and strengthened its presence in next-generation memory solutions market. The form factor of the sample is EDSFF (Enterprise &amp; Data Center Standard Form Factor) E3.S and it supports PCIe 5.0 x8 Lane, uses DDR5 standard DRAM and is equipped with CXL controllers.<\/p>\n<p>CXL<sup style=\"color: #ff0000;\">* <\/sup>, which is based on PCIe (Peripheral Component Interconnect Express)<sup style=\"color: #ff0000;\">* <\/sup>, is a new standardized interface that helps increase the efficiency of utilizing CPUs, GPUs, accelerators, and memory. SK hynix has participated in the CXL consortium from an early stage, and is looking to secure CXL memory market leadership.<\/p>\n<p class=\"footnote\"><sup style=\"color: #ff0000;\">* <\/sup>CXL (Compute Express Link): Next-generation interface to utilize high performance computing system efficiently.<br \/>\n<sup style=\"color: #ff0000;\">* <\/sup>PCIe (Peripheral Component Interconnect Express): Serial-structured high-speed input\/output interface used in the main boards of digital devices.<\/p>\n<p>\u00a0<\/p>\n<div style=\"text-align: center;\">\n<div style=\"display: inline-block; max-width: 748px; width: 100%; text-align: left;\">\n<div style=\"height: 2px; background: #666666; margin-bottom: 6px;\"><\/div>\n<h3 class=\"sub-title\" style=\"margin: 0; line-height: 1.4;\">Expandable CXL Memory to Begin Mass Production in 2023<\/h3>\n<div style=\"height: 2px; background: #666666; margin-top: 6px;\"><\/div>\n<\/div>\n<\/div>\n<div class=\"carousel-slider-wrapper\"><div class=\"carousel-slider-outer carousel-slider-outer-image-carousel carousel-slider-outer-8964 swiper navigation-visibility-always navigation-position-inside pagination-visibility-always pagination-shape-circle pagination-align-center\" style=\"--carousel-slider-nav-color:#f1f1f1;--carousel-slider-active-nav-color:#00d1b2;--carousel-slider-arrow-size:48px;--carousel-slider-bullet-size:10px;--swiper-theme-color:#f1f1f1;--swiper-navigation-size:48px;--swiper-pagination-bullet-size:10px\">\n<div id=\"&#039;id-8964\" class=\"carousel-slider carousel-slider-8964 arrows-visibility-always dots-visibility-always arrows-inside dots-center dots-circle swiper-wrapper\" data-slide-type=\"image-carousel\" data-swiper='{\"navigation\":{\"nextEl\":\".swiper-button-next\",\"prevEl\":\".swiper-button-prev\"},\"pagination\":{\"el\":\".swiper-pagination\",\"type\":\"bullets\",\"clickable\":true},\"direction\":\"horizontal\",\"loop\":true,\"slidesOffsetBefore\":0,\"slidesOffsetAfter\":0,\"speed\":500,\"spaceBetween\":10,\"slidesPerView\":1,\"autoplay\":{\"delay\":5000,\"pauseOnMouseEnter\":true}}'>\n<div class=\"swiper-slide\"><div class=\"carousel-slider__item\">\n\t<img loading=\"lazy\" decoding=\"async\" width=\"1000\" height=\"660\" src=\"https:\/\/d18r0a86za96sg.cloudfront.net\/wp-content\/uploads\/2026\/06\/13222257\/SK-hynix_CXL-01.png\" class=\"attachment-full size-full\" alt=\"\" srcset=\"https:\/\/d18r0a86za96sg.cloudfront.net\/wp-content\/uploads\/2026\/06\/13222257\/SK-hynix_CXL-01.png 1000w, https:\/\/d18r0a86za96sg.cloudfront.net\/wp-content\/uploads\/2026\/06\/13222257\/SK-hynix_CXL-01-300x198.png 300w, https:\/\/d18r0a86za96sg.cloudfront.net\/wp-content\/uploads\/2026\/06\/13222257\/SK-hynix_CXL-01-768x507.png 768w\" sizes=\"auto, (max-width: 1000px) 100vw, 1000px\" \/><\/a><\/div>\n<\/div>\n<div class=\"swiper-slide\"><div class=\"carousel-slider__item\">\n\t<img loading=\"lazy\" decoding=\"async\" width=\"1000\" height=\"660\" src=\"https:\/\/d18r0a86za96sg.cloudfront.net\/wp-content\/uploads\/2026\/06\/13222258\/SK-hynix_CXL-02.png\" class=\"attachment-full size-full\" alt=\"\" srcset=\"https:\/\/d18r0a86za96sg.cloudfront.net\/wp-content\/uploads\/2026\/06\/13222258\/SK-hynix_CXL-02.png 1000w, https:\/\/d18r0a86za96sg.cloudfront.net\/wp-content\/uploads\/2026\/06\/13222258\/SK-hynix_CXL-02-300x198.png 300w, https:\/\/d18r0a86za96sg.cloudfront.net\/wp-content\/uploads\/2026\/06\/13222258\/SK-hynix_CXL-02-768x507.png 768w\" sizes=\"auto, (max-width: 1000px) 100vw, 1000px\" \/><\/a><\/div>\n<\/div>\n<\/div><!-- .carousel-slider-8964 -->\n<div class=\"swiper-pagination\"><\/div><div class=\"swiper-button-prev\"><\/div><div class=\"swiper-button-next\"><\/div><\/div><!-- .carousel-slider-outer-8964 --><\/div>\n\n<p>The essential point of the CXL memory market is expandability. The CXL memory allows for flexible memory expansion compared to current server market, where the memory capacity and performance are fixed once the server platform is adopted. CXL also has high growth potential as it is an interface spotlighted for high performance computing systems such as AI and big data related applications.<\/p>\n<p>The first CXL memory device developed by SK hynix is a 96GB product composed of 24Gb DDR5 DRAMs based on 1anm, which is the latest tech node. The company expects high customer satisfaction of this product with flexible configuration of bandwidth and capacity expanded cost-efficiently.<\/p>\n<p>\u201cI see CXL as a new opportunity to expand memory and create a new market,\u201d said Uksong Kang, Head of DRAM Product Planning explaining SK hynix\u2019s CXL memory deployment strategy. \u201cWe aim to mass-produce CXL memory products by 2023, and will continue to develop cutting-edge DRAM technologies and advanced packaging technologies to launch various CXL-based bandwidth\/capacity expandable memory solution products.\u201d<\/p>\n<p>\u00a0<\/p>\n<div style=\"text-align: center;\">\n<div style=\"display: inline-block; max-width: 748px; width: 100%; text-align: left;\">\n<div style=\"height: 2px; background: #666666; margin-bottom: 6px;\"><\/div>\n<h3 class=\"sub-title\" style=\"margin: 0; line-height: 1.4;\">Various Collaboration Plans to Expand the CXL Memory Ecosystem<\/h3>\n<div style=\"height: 2px; background: #666666; margin-top: 6px;\"><\/div>\n<\/div>\n<\/div>\n<p><img loading=\"lazy\" decoding=\"async\" class=\"alignnone size-full wp-image-9579\" src=\"https:\/\/d18r0a86za96sg.cloudfront.net\/wp-content\/uploads\/2026\/05\/27174726\/SK-hynix_CXL_v02_02-2.png\" alt=\"\" width=\"1000\" height=\"600\" \/><\/p>\n<p>\u201cDell has been at the forefront of developing the CXL and EDSFF ecosystems, driving technology standards through the CXL and SNIA consortiums, and working closely with our partners on CXL product requirements to meet future workload demands. The SK hynix EDSFF E3.S form factor CXL memory module is an example of the innovative products that customers will be able to deploy to meet their growing memory needs,\u201d said Stuart Berke, Vice President and Fellow at Dell\u2019s Infrastructure Solutions Group.<\/p>\n<p>Dr. Debendra Das Sharma, Intel Senior Fellow and co-GM of Memory and I\/O Technologies at Intel added, \u201cCXL plays an essential role in extending memory for data center systems to evolve. We look forward to building and expanding the CXL memory ecosystem, as well as quickly developing technology standards through the CXL consortium, by collaborating with partners like SK hynix.\u201d<\/p>\n<p>\u201cAMD is excited about the possibilities of workload performance acceleration with memory expansion using CXL technology. We look forward to collaborating with SK hynix on the development and validation of CXL as the industry shifts to a more dynamic and flexible memory infrastructure,\u201d said Raghu Nambiar, Corporate Vice President of Data Center Ecosystems and Solutions at AMD.<\/p>\n<p>\u201cCXL is a key technology that will be critical in optimizing memory systems in the future, and we are actively working with SK hynix in CXL memory design and verification to promote the rapid development of the CXL memory ecosystem,\u201d said Christopher Cox, Vice President of Technology at Montage Technologies.<\/p>\n<p>\u00a0<\/p>\n<div style=\"text-align: center;\">\n<div style=\"display: inline-block; max-width: 748px; width: 100%; text-align: left;\">\n<div style=\"height: 2px; background: #666666; margin-bottom: 6px;\"><\/div>\n<h3 class=\"sub-title\" style=\"margin: 0; line-height: 1.4;\">Securing Technology Accessibility by Developing HMSDK dedicated to CXL Memory<\/h3>\n<div style=\"height: 2px; background: #666666; margin-top: 6px;\"><\/div>\n<\/div>\n<\/div>\n<p>SK hynix also developed the Heterogeneous Memory Software Development Kit (HMSDK)<sup style=\"color: #ff0000;\">* <\/sup> exclusively for CXL memory devices. The kit will include features to improve system performance and monitor the systems while running various workloads. The company plans to distribute it as an open source in the fourth quarter of 2022. It is expected that end users such as software developers will be able to utilize SK hynix\u2019s CXL memory more effectively.<\/p>\n<p class=\"footnote\"><sup style=\"color: #ff0000;\">* <\/sup>HMSDK (Heterogeneous Memory Software Development Kit): A software development kit that allows different grades of memory to be operated in one system.<\/p>\n<p>The company prepared a separate sample for evaluation to help customers evaluate it with ease. As there is currently no server which supports EDSFF E3.S x8 Lane, SK hynix replaced the dedicated samples\u2019 EDSFF pins with PCIe to support customers install the samples to existing PCIe slots.<\/p>\n<p>SK hynix is planning to exhibit the product in upcoming events, beginning with Flash Memory Summit in early August, Intel Innovation at the end of September and Open Compute Project (OCP) Global Summit in October, while scheduling to demonstrate a demo with HMSDK as well. The company will actively deploy CXL memory related business to provide customers with the memory products they need in a timely manner.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>SK hynix develops its first DDR5 DRAM-based CXL sample Expandable CXL memory to secure the technology accessibility by development of dedicated HMSDK SK hynix to expand the CXL memory ecosystem while strengthening its presence in the next-gen memory solutions market SK hynix Inc. (or \u201cthe company\u201d, www.skhynix.com) has developed its first DDR5 DRAM-based CXL (Compute [\u2026]<\/p>\n","protected":false},"author":23,"featured_media":3172,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"_migrated_source_id":9562,"footnotes":"","_members_access_role":[],"_members_access_error":""},"categories":[5],"tags":[1415,155,157,51,878],"class_list":["post-3177","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-tech-and-ai","tag-collaboration","tag-cxl","tag-ddr5","tag-dram","tag-product-planning","series-global-ai-company-cxl"],"acf":[],"_links":{"self":[{"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/posts\/3177","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/users\/23"}],"replies":[{"embeddable":true,"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/comments?post=3177"}],"version-history":[{"count":2,"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/posts\/3177\/revisions"}],"predecessor-version":[{"id":8968,"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/posts\/3177\/revisions\/8968"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/media\/3172"}],"wp:attachment":[{"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/media?parent=3177"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/categories?post=3177"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/tags?post=3177"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}