{"id":4341,"date":"2020-10-06T02:00:20","date_gmt":"2020-10-06T02:00:20","guid":{"rendered":"http:\/\/localhost:8080\/sk-hynix-launches-worlds-first-ddr5-dram\/"},"modified":"2026-06-09T11:13:35","modified_gmt":"2026-06-09T11:13:35","slug":"sk-hynix-launches-worlds-first-ddr5-dram","status":"publish","type":"post","link":"https:\/\/news.skhynix.com\/en\/sk-hynix-launches-worlds-first-ddr5-dram\/","title":{"rendered":"SK hynix Launches World\u2019s First DDR5 DRAM"},"content":{"rendered":"

Seoul, October 6, 2020<\/strong>
\nSK hynix Inc. (or \u2018the Company,\u2019 www.skhynix.com<\/a>) announced to launch world\u2019s first DDR5 DRAM. It is a high-speed and high-density product optimized for Big Data, Artificial Intelligence (AI), and machine learning (ML) as a next generation standard of DRAM.<\/p>\n

Since SK hynix announced the development of World\u2019s First 16 Gigabit (Gb) DDR5 DRAM on November 2018, the Company has provided its major partners including Intel with sample products, and has completed various tests and verification of its functions and compatibility. This will allow SK hynix to provide its customers with the products once the DDR5 market becomes active.<\/p>\n

In the meantime, SK hynix has conducted joint-operation of on-site lab, system-level test, and simulation with System-on-Chip*<\/span>) (SoC) manufacturers to verify the functions of DDR5. Also, the Company validated compatibility of its DDR5 and the major components on DRAM module including register clock driver*<\/span>) (RCD), which affect DRAM performance, and power management integrated circuit*<\/span>) (PMIC). Through these verifications, SK hynix has been collaborating closely with its global partners.<\/p>\n

SK hynix\u2019s DDR5 supports transfer rate of 4,800 ~ 5,600 Megabit-per-second (Mbps), which is 1.8 times faster than the previous generation \u2013 DDR4. It can transmit 9 full-HD (FHD) movies (5GB each) per second with 5,600Mbps transfer rate. Its operating voltage is 1.1V being lowered from 1.2V of DDR4, which means that its power consumption is reduced by 20%.<\/p>\n

Another notable specification of the Company\u2019s DDR5 is Error Correcting Code (ECC) inside the chip that can correct even 1-bit-level errors by itself. With the ECC, the reliability of applications will be increased by 20 times. The Company\u2019s DDR5 also could build up to 256 Gigabyte (GB) capacity applying through-silicon-via (TSV) technology.<\/p>\n

The Company expects that these eco-friendly semiconductor memories will reduce both the power consumption and operating costs of data centers as DDR5 consumes less power and significantly improves its reliability.<\/p>\n

\u201cIntel partnered closely with memory leaders including SK hynix on the DDR5 spec development starting with early architecture concepts through JEDEC standardization,\u201d commented Carolyn Duran, Vice President of Intel\u2019s Data Platforms Group and GM of Memory and IO Technologies. \u201cIn addition, we worked collaboratively with SK hynix on silicon development by designing and testing prototypes to ensure DDR5 meets its performance goals and are fully ready for our mutual customers.\u201d<\/p>\n

\u201cAs SK hynix has launched World\u2019s First DDR5 DRAM, the Company could lead the future technology trend in global DRAM market,\u201d said Jonghoon Oh, Executive Vice President and Chief Marketing Officer (CMO) at SK hynix. \u201cSK hynix will focus on the fast-growing premium server market, solidifying its position as a leading company in server DRAM.\u201d<\/p>\n

Meanwhile, DDR5 standard was published by JEDEC<\/a> (JEDEC Solid State Technology Association) earlier on July, 2020. According to market intelligence provider Omdia, the DDR5 demand will begin its surge in 2021, and it will possess 10% of total global DRAM market in 2022 and increase to 43% in 2024.<\/p>\n

Synopsys, Renesas, Montage Technology, and Rambus have also stated their commitment to the continuing cooperation in creating the DDR5 ecosystem.<\/p>\n

\u201cSynopsys has collaborated with SK hynix to deliver highly reliable DDR5 solutions for advanced high-performance computing SoCs requiring ultra-fast and high-capacity memory subsystems,\u201d said John Koeter, senior vice president of marketing and strategy for IP at Synopsys. \u201cOur silicon-proven DesignWare DDR5\/4 IP has been validated using numerous SK hynix DDR5 RDIMMs at up to 6400 Mbps, helping designers minimize risk and meet their high-performance requirements of data-intensive SoCs.\u201d<\/p>\n

\u201cAs the leading supplier of memory interface products for every generation of memory over the last twenty years, we pride ourselves on strong engagements with our key partners and customers. Renesas has worked closely with SK hynix to qualify a complete portfolio of DDR5 products for server, client and embedded markets.\u201d Rami Sethi \u2013 Vice President and General Manager of Renesas\u2019 Data Center Business Division<\/p>\n

\u201cMontage Technology is thrilled to partner with SK hynix on enabling the DDR5 memory ecosystem. As a leading vendor, we have been collaborating with SK hynix through many DDR generations, and are committed to providing high-performance, low-power memory interface solutions. Currently, Montage Technology offers a comprehensive portfolio of DDR5 logic devices \u2013 we are excited to further help SK hynix accelerate DDR5 market adoption,\u201d Geof Findley, VP of Sales and Business Development at Montage Technology<\/p>\n

\u201cCompute-intensive workloads in the data center are accelerating the need for greater memory capacity and bandwidth,\u201d said\u202fChien-Hsin Lee, vice president and general manager, Integrated Circuits at Rambus. \u201cDDR5 DRAM answers the call with higher data rates and new innovations that dramatically boost memory performance. Employing a new generation of memory interface chips, DDR5 RDIMMs and LRDIMMs will unleash the processing power of server platforms. We are pleased to partner with SK hynix to enable next-generation technology for the ecosystem and fulfill the growing demand for DDR5.\u201d<\/p>\n

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Annotation<\/strong>
\n\u25a0 SoC (System on Chip)
\nA single chip solution integrating peripherals that interlock to the system bus and the central processing unit (CPU).<\/p>\n

\u25a0 RCD(Register Clock Driver)
\nAn active element that is used in RDIMM and LRDIMM for servers, which ensures signal quality between the transmitter and the receiver by amplifying commands and data signals applied to memory from memory controllers.<\/p>\n

\u25a0 PMIC (Power Management Integrated Circuit)
\nAn integrated circuit that receives the main power input and rectifies, divides and controls it into a stable and efficient voltage or current required by the electronics; PMIC is adopted in DDR5 DRAM module for the first time.<\/p>\n

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About SK hynix Inc.<\/strong>
\nSK hynix Inc., headquartered in Korea, is the world\u2019s top tier semiconductor supplier offering Dynamic Random Access Memory chips (\u201cDRAM\u201d), flash memory chips (\u201cNAND flash\u201d) and CMOS Image Sensors (\u201cCIS\u201d) for a wide range of distinguished customers globally. The Company\u2019s shares are traded on the Korea Exchange, and the Global Depository shares are listed on the Luxemburg Stock Exchange. Further information about SK hynix is available at www.skhynix.com<\/a>, news.skhynix.com<\/a>.<\/p>\n

\u00a0<\/p>\n

Media Contact<\/strong>
\nSK hynix Inc.
\nGlobal Public Relations<\/p>\n

Technical Leader
\nSejin Julia Yoo
\nE-Mail: global_newsroom@skhynix.com<\/a><\/p>\n

Technical Leader
\nJaehwan Kevin Kim
\nE-Mail: global_newsroom@skhynix.com<\/a><\/p>\n

Technical Leader
\nEun Suk Yixi Lee
\nE-Mail: global_newsroom@skhynix.com<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"

Seoul, October 6, 2020 SK hynix Inc. (or \u2018the Company,\u2019 www.skhynix.com) announced to launch world\u2019s first DDR5 DRAM. It is a high-speed and high-density product optimized for Big Data, Artificial Intelligence (AI), and machine learning (ML) as a next generation standard of DRAM. Since SK hynix announced the development of World\u2019s First 16 Gigabit (Gb) [\u2026]<\/p>\n","protected":false},"author":23,"featured_media":4337,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"_migrated_source_id":5744,"footnotes":"","_members_access_role":[],"_members_access_error":""},"categories":[4],"tags":[157,363,388],"class_list":["post-4341","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-press","tag-ddr5","tag-skhynix","tag-worldsfirst"],"acf":[],"_links":{"self":[{"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/posts\/4341","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/users\/23"}],"replies":[{"embeddable":true,"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/comments?post=4341"}],"version-history":[{"count":3,"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/posts\/4341\/revisions"}],"predecessor-version":[{"id":6358,"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/posts\/4341\/revisions\/6358"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/media\/4337"}],"wp:attachment":[{"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/media?parent=4341"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/categories?post=4341"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/tags?post=4341"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}