{"id":4549,"date":"2020-06-18T02:53:12","date_gmt":"2020-06-18T02:53:12","guid":{"rendered":"http:\/\/localhost:8080\/diversification-of-dram-application-and-memory-hierarchy\/"},"modified":"2026-07-29T15:02:52","modified_gmt":"2026-07-29T06:02:52","slug":"diversification-of-dram-application-and-memory-hierarchy","status":"publish","type":"post","link":"https:\/\/news.skhynix.com\/en\/diversification-of-dram-application-and-memory-hierarchy\/","title":{"rendered":"Diversification of DRAM Application and Memory Hierarchy"},"content":{"rendered":"

Installed in various application devices like PCs, servers, smartphones and gaming devices, Dynamic Random Access Memory, or DRAM, plays the role of main memory, which is responsible for the storage of data processed by CPU operations.<\/p>\n

DRAMs fall under the larger category of Random Access Memories, or RAMs, which process data access randomly. Out of this group, the structure of DRAM is the simplest, allowing for high capacity, rapid read and write speed, and cost competitiveness. It is for these reasons that DRAMs are so popular in today\u2019s market. However, a DRAM\u2019s simple structure also means that data is stored within a capacitor, where data slowly exhausts over time. To manage this volatility, DRAMs require periodic data charging called \u2018refresh.\u2019<\/p>\n

In general, DRAMs are classified into several fields, each evolving into their own optimized forms. This article will explore the growing fields of computing, mobile and graphic application memories.<\/p>\n

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Computing Memory<\/h3>\n
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Computing memories used in PCs and servers are evolving high performance and high capacity data processing. Initially, Single Data Rate (SDR) DRAMs were used to send or receive just one data during one period of CPU system clock. As the CPU\u2019s processing speed increased however, DRAM required faster processing speeds as well as higher memory bandwidth to keep up. Since then, the industry has advanced to Double Data Rate (DDR) DRAMs, which can process the data twice as fast \u2013 two times per one period . Over the years, the industry has iterated newer, faster products like DDR2, DDR3, DDR4, and DDR5, which have continued to accelerate clock speed.<\/p>\n

In order to accommodate higher-capacity memory for servers, many are now using a Dual In-line Memory Module (DIMM) where multiple DRAM chips are mounted on a circuit board. Due to international standards and a long-established system configuration, DIMM has seen limited changes in form factors and power requirements over recent years.<\/p>\n

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\u25b2 Table 1. Specifications of Computing Memory<\/p>\n

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\u25b2 Figure 1. DDR5 Module by SK hynix<\/p>\n

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Mobile Memory<\/h3>\n
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The explosive growth of mobile markets such as mobile phones and tablets has contributed to the development of the mobile application memory field. In mobile devices, battery power is essential. That\u2019s why the industry developed Low Power Double Data Rate (LPDDR) DRAMs, low-power memory products that minimize battery consumption by reducing the leakage current in standby mode. Just like DDRs, LPDDRs have seen many iterations over the years. The LPDDR DRAM has evolved into LPDDR2, LPDDR3, LPDDR4, and LPDDR5 DRAMS, with each generation\u2019s clock speed doubled and power efficiency improved, which is represented by power consumption over bandwidth.<\/p>\n

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\u25b2 Table 2. Specifications of Mobile Memory<\/p>\n

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\u25b2 Figure 2. LPDDR4(X) by SK hynix<\/p>\n

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Graphic Memory<\/h3>\n
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Graphics Processing Unit (GPU) is specialized in parallel data processing. One memory chip is allocated to each GPU core, creating a channel which allows parallel processing. So in a multi-core structure, the bandwidth of each memory chip dictates system performance. The higher the bandwidth, the better the performance. To manage this, Graphics Double Data Rate (GDDR) memories, optimized for parallel operation applications, have been developed. Over the years, as demand for better bandwidth increased,they have evolved into GDDR2, GDDR3, GDDR4, GDDR5, and GDDR6.<\/p>\n

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\u25b2 Table 3. Specifications of Graphic Memory<\/p>\n

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\u25b2 Figure 3. GDDR6 by SK hynix<\/p>\n

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Memory Hierarchy<\/h3>\n
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As seen in all of these series \u2013 from DDR to LPDDR and GDDR \u2013 DRAMs have been diversified greatly over time. Recently however, this evolution has slowed, with the improvement of performance and capacity becoming an increasingly difficult task.<\/p>\n

To overcome this, the development of DRAMs is forging a new path through diversification of memory hierarchy. This \u201crevolutionary path\u201d has two directions: High Bandwidth Memory and High Capacity Memory.<\/p>\n

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\u25b2 Figure 4. Revolutionary Path and Evolutionary Path<\/p>\n

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\u25b2 Figure 5. Memories for the Revolutionary Path<\/p>\n

\u203b Reference. Revolutionary Path and Evolutionary Path (Source: Presentation material \u201cTechnology Scaling Challenges and Opportunities of Memory Devices\u201d by CEO Seok-hee Lee, at IEDM)<\/em><\/p>\n

To deal with the demand for a larger bandwidth, High Bandwidth Memory (HBM) delivers a new tier between the last level cache of CPU and DRAM . Based on Through Silicon Via (TSV) technology, HBM has been developed to establish next-generation. HBM is mainly used in graphics, network, and HPC (high performance computing).<\/p>\n

While it has advantages in high bandwidth and applicability compared to GDDR, it has some disadvantages in price, capacity, and application difficulty as well. That\u2019s why many graphic card manufacturers are selectively adopting GDDR and HBM according to the application fields. Given the role of GPUs in the deep neural network field for artificial intelligence (AI) and machine learning (ML), GDDR and HBM are also expanding their application range into these areas.<\/p>\n

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\u25b2 Table 4. Specifications of High Bandwidth Memory<\/p>\n

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\u25b2 Figure 6. HBM2E by SK hynix<\/p>\n

Meanwhile, a High Capacity Memory (HCM) delivers a new tier between DRAM and NAND Flash. As regard for the High Capacity Memory, there are two commercially developed solutions. One is a managed DRAM solution, which combines DRAM and a memory controller that improves internal timing for the expansion of capacity. The other one is equipped with a storage class memory such as Phase Change Memory (PCM), which has advantages in density compared to DRAM. High Capacity Memory is provided to customers in the form of a solution combined with a controller to ensure reliability, availability, and serviceability (RAS).<\/p>\n

In the system industry, there have been various movements to utilize HCM. In particular,Compute Express Link (CXL), open interconnect consortium created primarily by Intel in 2019 has been driving discussions for actual adoption of HCMs in major data centers, servers, and SoC providers.<\/p>\n

Along with HBM and HCM, the need for memories in autonomous vehicles and AI\/ML application will likely increase as well. This change may be an opportunity for memory manufacturers to expand the market. At the same time, however, the pressure to develop products and the demand in new technologies increase simultaneously in order to correspond to the diversifying market.<\/p>\n

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Future Memory<\/h3>\n
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SK hynix is focusing on developing advanced technologies to cope with memory technology changes. Also, the company is working with leading ICT (Information & Communication Technology) companies to make our lives more convenient. This work will act as a catalyst for the development of cutting-edge technologies that contribute to the progress of mankind.<\/p>\n


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Junhyun Chun<\/p>\n

Vice President, Head of DRAM Design at SK hynix Inc..<\/span><\/p>\n<\/div>\n<\/div>\n

<\/p>\n","protected":false},"excerpt":{"rendered":"

Installed in various application devices like PCs, servers, smartphones and gaming devices, Dynamic Random Access Memory, or DRAM, plays the role of main memory, which is responsible for the storage of data processed by CPU operations. DRAMs fall under the larger category of Random Access Memories, or RAMs, which process data access randomly. Out of [\u2026]<\/p>\n","protected":false},"author":23,"featured_media":4537,"comment_status":"closed","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"_migrated_source_id":5192,"footnotes":"","_members_access_role":[],"_members_access_error":""},"categories":[5],"tags":[1270,51,1268,208,1269,1267],"class_list":["post-4549","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-tech-and-ai","tag-computing-memory","tag-dram","tag-dram-application","tag-graphic-memory","tag-memory-hierarchy","tag-mobile-memory"],"acf":[],"_links":{"self":[{"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/posts\/4549","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/users\/23"}],"replies":[{"embeddable":true,"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/comments?post=4549"}],"version-history":[{"count":4,"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/posts\/4549\/revisions"}],"predecessor-version":[{"id":11968,"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/posts\/4549\/revisions\/11968"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/media\/4537"}],"wp:attachment":[{"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/media?parent=4549"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/categories?post=4549"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/news.skhynix.com\/en\/wp-json\/wp\/v2\/tags?post=4549"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}