Head of DRAM PE Joohwan Cho, Key Person of the Development of the World’s First 40nm-class 2Gb Graphic DDR5
  • Culture & People

Head of DRAM PE Joohwan Cho, Key Person of the Development of the World’s First 40nm-class 2Gb Graphic DDR5

A New Attempt for the High-Speed One day in 2008, the performance test for the graphic DRAM was in full...
The Innovator – Viktar Zaitsau, Leader of Design Verification Team
The Visual Evolution & Innovation of Image Sensors
  • Opinion

The Visual Evolution & Innovation of Image Sensors

Visual Evolution – from the Cambrian Era to Today. Close your eyes and imagine a world without eyesight. Millions of...

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Event
October 28, 2020

Q3 2020 Earnings Conference Call Invitation

SK hynix Inc. will present its third quarter earnings of 2020 on Nov. 4th, 2020 (Wednesday). Announcement of the earnings in a press release will be made before 9:00 a.m.…
Press Releasefeatured
October 20, 2020

SK hynix to Acquire Intel NAND Memory Business

NEWS HIGHLIGHTS SK hynix will pay US $9 billion for the Intel NAND memory and storage business, which includes the NAND SSD business, the NAND component and wafer business, and…
Press Release
October 6, 2020

SK hynix Launches World’s First DDR5 DRAM

Seoul, October 6, 2020 SK hynix Inc. (or ‘the Company,’ www.skhynix.com) announced to launch world’s first DDR5 DRAM. It is a high-speed and high-density product optimized for Big Data, Artificial…

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Opinionfeatured
October 28, 2020

The Visual Evolution & Innovation of Image Sensors

Visual Evolution – from the Cambrian Era to Today. Close your eyes and imagine a world without eyesight. Millions of years ago, that was the way of life on Earth.…
Technologyfeatured
October 15, 2020

[Invisible Memory : Part.3] Semiconductor Memory in Our Smart Cities


Business
October 7, 2020

Celebrating our global newsroom’s first anniversary

It’s been one year since SK hynix launched its global newsroom in October 2019 with the goal of creating a central hub for thought leadership, conversation, and industry insights across…

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Culture & Peoplefeatured
October 29, 2020

Head of DRAM PE Joohwan Cho, Key Person of the Development of the World’s First 40nm-class 2Gb Graphic DDR5

A New Attempt for the High-Speed One day in 2008, the performance test for the graphic DRAM was in full swing at the Design Analysis Office at SK hynix (Hynix…
Culture & Peoplefeatured
October 28, 2020

The Innovator – Viktar Zaitsau, Leader of Design Verification Team


Culture & People
October 22, 2020

People who Create the Value of DRAM Products with High Technical Competitiveness: D-TEST Technology

Image Download Responsible for the Quality of DRAM through Complete Testing and Defect Analysis The semiconductor process can be largely divided into a front-end process and a back-end process. The…

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