Miniaturization has played a significant role in the advancement of the semiconductor industry. Memory manufacturers have used miniaturization technology, which involves fitting more transistors on smaller chips, to improve the efficiency and performance of their products. However, this process of shrinking devices causes issues such as increased interference between electrons, current leakage, and heat generation. Consequently, miniaturization has become increasingly difficult and the pace of its progress has slowed down.
The industry’s solution to these limitations was found in a back-end packaging technology which offered enhancements in performance, efficiency, and capacity. Referred to as advanced packaging technology, it revolutionized heterogeneous integration that brings together different types of chips, such as DRAM and NAND, and increased bandwidth by stacking DRAMs vertically.
Heterogeneous Integration Spurred on by Advanced Packaging Technologies
While SK hynix has continued to introduce its next-generation semiconductors at several domestic and global conferences, the company’s key focus has been on heterogeneous integration, which involves the integration of semiconductor memory and logic semiconductors.
This is the idea of bringing together different chips in close proximity with each other to minimize the traveling paths for data used in computations, resulting in a single package with advanced performance and efficiency. Known as a system-in-package (SiP)1, it fundamentally needs miniaturization as well as advanced packaging technology.
1 System-in-package (SiP): Multiple integrated circuits bundled into a single package, capable of performing all or most of the functions of an electronic system.
SK hynix considers the next 40 years as the era of heterogeneous integration, which is why it continues to focus on developing advanced packaging technologies to introduce new products with high performance and capacity. Chiplet, multi-chip packaging (MCP), vertical wire fan-out (VFO), and advanced mass reflow-molded underfill (MR-MUF) are some of the main technologies for heterogeneous integration. In this second episode in our Tech Pathfinder series, it will explain in detail these technologies’ concepts, processes, benefits, and applications.
Chiplets: Breaking Down Chips to Incorporate Their Functions in One Package
Semiconductors are made up of components with different functions. A CPU alone is a combination of computation, storage, power, and data input/output (I/O) functions. Likewise, a semiconductor is the end result of fabricating various components at once and packaging them all together.
While it was common to make semiconductors this way in the past, problems started to arise with the continuation of miniaturization and the need to consistently improve performance. If each chip with a distinct function is compared to a candy and the semiconductor is a candy gift basket, the volume of the gift basket will keep increasing as more candies are added. To accommodate this growing number of candies, the internal arrangements of the gift box will also become more complex. If a candy breaks, the inside of the gift basket would be filled with crumbs and the whole gift basket would lose value. The same applies to a semiconductor that features a bad device.
As the semiconductor industry started to think about solutions to this problem, a question arose: what if the devices were made and packaged separately? Thus, the solution was to fabricate each area of the semiconductor separately. This is known as chiplet technology which divides a monolithic chip by function and puts it back together again. In other words, chips that are fabricated for computation, storage, power, data entry, and other functions are made and packaged separately. Lastly, they are combined at the packaging stage of the back-end process. The separated chip pieces are called chiplets, and they can be freely arranged and assembled in any way much like Lego blocks.
Chiplets offer a range of advantages. As the chips are broken down into smaller pieces, the entire chip does not need to be discarded due to a bad device in a particular area. Just the individual chiplets can be replaced with a new chiplet that has already been fabricated. In addition, since chiplets are made from multiple small dies2, more net dies can be produced on a wafer which results in higher yields. Lastly, different processes can be applied to chiplets. For example, core chiplets can be made with a 10 nanometer (nm) process, while other chiplets can be made with a 20nm process. Thus, the development efficiency and costs can be controlled by focusing resources only to chiplets that require high performance. Returning to the candy analogy, simple candies can be made on a relatively inexpensive machine but those which require more complex processes such as adding chocolate must be made on a more expensive machine. This feature of chiplets has made it possible to fabricate semiconductors at a lower cost and with higher efficiency.
2 Die: Each chip is referred to as a die before it is cut from the wafer.
▲ Figure 1. The process of packaging chiplets and its advantages
As shown in Figure 1, the basic concept of a chiplet is to combine devices a-1 and a-2 that possess different functions. Chips that are separated by function are interconnected on a substrate to become 2D, 2.5D, or 3D structures. Different chips are stacked horizontally in a 2D structure, while a 3D structure features vertically stacked chips. Meanwhile, a 2.5D structure includes an RDL interposer3 inserted between a 2D chiplets and a substrate. This silicon circuit board is thinner than the substrate and has data I/O terminals with a higher density. This means that the data paths are densely packed. An RDL interposer can be likened to a bike path next to a sidewalk that allows cyclists to travel faster. Since high-performance circuits like this can achieve faster data speeds, they are referred to as 2.5D despite technically being 2D.
Meanwhile, SK hynix is developing chiplet technology to be applied to its CXL4 memory controllers. The controller chiplets are each placed at the minimum distance of 2.5D from targets they correspond with, and this structure is expected to improve communication speeds and memory scalability. Accordingly, CXL memory with chiplets is set to be a significant solution in the era of big data and AI, and will act as a pillar in future high-performance computing systems.
3 Redistribution layer (RDL) interposer: The construction of a new circuit in the middle to electrically connect a smaller semiconductor circuit with a larger substrate circuit.
4 Compute Express Link (CXL): A PCIe-based, next-generation interconnect protocol for efficiently building high-performance computing systems. Enables more efficient integrated utilization of various solutions such as memory, GPUs, AI accelerators, etc.
Multi-Chip Package (MCP): Bringing Memory Chips Together for High-Performance Products
Multi-chip package (MCP) is a technology that vertically stacks multiple memory chips into one package. While MCP may sound similar to chiplets, there are fundamental differences between the two. For one, MCP specializes in memory products like NAND and DRAM, and the combination of these two products can make an MCP. For one, MCP specializes in stacking memory products like NAND and DRAM, stacks NAND and DRAM, which are thin chips with completely different properties. In the past, a package stacked with multiple homogeneous chips was considered to be an MCP, but it is more common these days for an MCP to combine multiple heterogeneous chips.
Efficiency enhancement and mobile optimization are the main reasons for stacking multiple chips. This is because chip stacking minimizes both power consumption and space taken by chips while maintaining a large capacity. This leads to the benefits of using MCPs. Firstly, even if numerous chips are in an MCP, the package will remain thin as MCPs are manufactured to a thickness standard of 1.4 mm or less as defined by microelectronics standards body JEDEC in response to customer and market trends. Hence, the thin and small chips in an MCP take up a minimal amount of space. Additionally, MCPs also simplify the process of attaching to a device. Compared to mounting NANDs and DRAMs separately on a device’s main printed circuit board (PCB), MCPs simplify the manufacturing process. Lastly, power efficiency is also improved by running multiple chips at once. For these reasons, MCPs are often used in mobile devices where smaller chips are preferred.
▲ Figure 2. The different methods of fabricating MCPs and their advantages
MCPs can consist of many different combinations of chips. For example, NANDs and DRAMs can be separately stacked on a substrate through planar vertical stacking or NANDs can be stacked on top of DRAMs through mixed vertical stacking. When MCPs are stacked like this, each chip is attached with a die attach film (DAF)5 and connected to the substrate with wires made of substances like gold, copper, and aluminum. The chips are then wrapped in a protective material that is made from epoxy mold compound (EMC)6 to complete the packaging process.
5 Die attach film (DAF): A thin adhesive film that protects the chip and bonds the semiconductor to the substrate.
6 Epoxy molding compound (EMC): An epoxy resin-based heat dissipation material capable of sealing the chip to protect it from external impacts like heat, moisture, and shock.
SK hynix has been fabricating MCPs for more than two decades. A key breakthrough was made in 2007 when the company introduced the world’s first 24-layer NAND MCP. Since then, it has been offering competitive MCP products through its sophisticated processes that are capable of controlling and stacking chips of 50 micrometers (μm) or less. SK hynix plans to continue developing these highly integrated products to increase profitability and meet the rising demand from global mobile markets.
Vertical Wire Fan-Out (VFO): Combining Fan-Out WLP With DRAM Stacking
Vertical wire fan-out (VFO) is based on the principle that it is quicker and shorter to travel along a straight line than a curved one. This applies to the wires that connect chips and circuit boards. Consequently, VFO is a technology that minimizes space and reduces power consumption by connecting wires vertically instead of curving them. It has also revolutionized the sizeable fan-out wafer-level package (WLP), a packaging technology which connects I/O terminals with wires from the outside of the chip.
The advantages of using fan-out WLP include the capability to develop thinner packages due to the lack of a substrate. It also offers improved electrical characteristics and higher thermal efficiency thanks to the reduced length of wiring between the chips and the main board. Moreover, the technology can be applied to high-performance products as it provides more data I/O points. However, despite its advanced characteristics, the use of fan-out WLP technology in semiconductor memories has been limited. The structure resulting from stacking chips and connecting them to a substrate with curved wires on either side did not turn out to be a good method for applying fan-out WLP to semiconductor memories.
The world’s first VFO developed by SK hynix overcomes this limitation. By utilizing vertical wires to connect stacked DRAMs, the company was able to realize the optimal fan-out WLP. These vertical wires changed the path that electrical signals travel along from long and curved to short and straight to increase the power efficiency. This can be compared to driving through a tunnel instead of driving around a mountain to get to the destination with less time and effort. These benefits were highlighted during IEEE Electron Devices Technology and Manufacturing (EDTM) 2023, later being mentioned as a memory technology that goes hand-in-hand with today’s mobile device trends.
▲Figure 3. The VFP process and its various benefits
Recently, SK hynix completed the development of VFO technology and started its verification process, and this led to significant results when applied to LPDDR products. Compared to products that use conventional wiring, the wire length was reduced 4.6 times and power efficiency improved by 4.9%. While heat dissipation also increased by 1.4%, the most noticeable advancement was the 27% reduction in package thickness.
In recent years, the industry has accelerated the adoption of fan-out WLP to keep pace with the high specifications of smartphones and to secure battery capacity in such devices by reducing the size of components. VFO will help SK hynix develop more mobile-optimized memory products to meet customer demands and contribute significantly to the global market.
Advanced Mass Reflow Molded Underfill (MR-MUF): Connecting Vertically Stacked Chips With Ease
It is important to understand the concept behind mass reflow-molded underfill (MR-MUF) before talking about advanced MR-MUF. Firstly, MR-MUF is a technology which is used to stack multiple chips and package them. It is used commonly in High Bandwidth Memory (HBM), which increases the number of data paths, or bandwidth, by stacking multiple DRAM chips with TSV7. The thousands of data paths that vertically run through the stacked chips are connected without wiring and are later wrapped with MR-MUF.
7 Through-silicon via (TSV): A type of vertical interconnect access (via) that completely passes through a silicon die or wafer to enable the stacking of silicon dice. SK hynix utilized TSV technology to develop HBM3 with data processing speeds up to 819 GB/s (819 gigabytes per second)
▲ Figure 4. Characteristics of advanced MR-MUF and its advantages
Ultimately, MR-MUF is the technology that can efficiently connect vertically stacked chips. This allows multiple chips to be packaged at once, making it an innovative technology for semiconductor processes that increases productivity and improves product reliability.
To better understand the process of MR-MUF, it will be helpful to separately look at the roles of mass reflow (MR) and molded underfill (MUF). When MR connects vertically stacked chips and circuits, a micro bump that acts as a bridge is placed underneath each chip’s connection passage. As the lead material in the bump melts, the top and bottom pathways of the chip are connected. Melting all of these bumps at once to connect the chip is called reflow. It adds the prefix “mass” to indicate that a large number of bumps are melted. Meanwhile, MUF is a technology used to protect chips by applying protective materials to external areas including between and around chips. The process of filling between chips with the protective material is called underfill and the method of wrapping the chips is known as molding8, and they are performed simultaneously.
8 Molding: The process of sealing wire-bonded or flip chip bonded semiconductor products with an epoxy molding compound (EMC).
So, why is it called “advanced” MR-MUF? It is because the technology improves existing shortcomings of MR-MUF. As reflow runs at high temperatures during MR-MUF, this causes warpage on the chip, making it challenging to apply an MR-MUF process in the past. Likewise, SK hynix continued using MR-MUF because of its advantages, but a problem arose when developing its 12-layer HBM3. Moreover, due to the chip having to be 40% thinner for 12-layer HBM3, it was necessary to develop new technologies to overcome warpage. In response, SK hynix introduced the industry’s first chip control technology and improved heat dissipation with new protective materials. The result of these two technologies is the advanced MR-MUF.
Chip control technology is implemented by applying a momentary burst of high heat to each chip as it is stacked. This causes the bump under the top chip to fuse to a thin pad on top of the bottom chip. The pad holds the chip together and prevents it from warpage. This process is repeated for each stack of chips. At the end of the process, the MR-MUF is finalized and the chip is packaged in a new protective material that provides better heat dissipation.
The reason SK hynix is continuing to utilize MR-MUF and even develop advanced related processes is because of its reliability and efficiency. MR-MUF follows the same principles of an oven that evenly distributes heat to food. Likewise, all the chips are heated and interconnected at once during MR-MUF. As the process simultaneously fills the protective material between the chips and packs the chip, it further increases the efficiency. In fact, SK hynix has seen a threefold improvement in productivity with this technology. For example, the 12-layer HBM3 improved heat dissipation by 36% compared to its predecessor.
This is how SK hynix developed its 24 GB 12-layer HBM3 that provides the largest capacity and highest performance, while maintaining the same thickness as its 16 GB 8-layer counterpart. Meanwhile, SK hynix also plans to advance its bonding technology and apply it to HBM products in the future. The company aims to strengthen its presence in the HBM market by developing new products through hybrid bonding, which interconnects data holes directly without bumps.
Taking Advanced Packaging Technology to the Next Level
In this episode of the Pathfinder series, we took a look at SK hynix’s advanced packaging technologies that innovatively solved the limitations of miniaturization. SK hynix has taken a step forward in the era of semiconductor convergence with advanced packaging technologies that include chiplets, MCP, VFO, and advanced MR-MUF, while actively developing products such as HBM, PIM, and CXL. More importantly, the company plans to even further enhance its advanced packaging technology to prepare for the upcoming era of heterogeneous integration.
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