Head of DRAM PE Joohwan Cho, Key Person of the Development of the World’s First 40nm-class 2Gb Graphic DDR5 October 29, 2020 STORY 40nm-class 2Gb Graphic DDR5 Behind-the-scenes Story GDDR5 Minterview
Key Person of the Development of 128GB DDR4 Module with the World’s First Maximum Capacity: Seon Soon Kim, Head of DRAM PI October 8, 2020 STORY 128GB DDR4 Module Behind-the-scenes Story interview
