How Selector-Only Memory Emerged as the Leading Solution for CXL

Since its release in 2019, Compute Express Link (CXL)¹ has emerged as an efficient interconnect for processors, memory expansion and accelerators in terms of power usage and resources. This is due to CXL’s ability to maintain memory coherency between the CPU and attached devices, enabling resource sharing for higher performance and lower overall system cost. As memory is required for optimizing performance and capacity in a CXL environment, manufacturers have been working to develop solutions suitable for this role. This article will introduce SK hynix’s selector-only memory (SOM), also known as self-selecting memory (SSM), which has surpassed rival solutions to emerge as a leading CXL memory in the AI era. In particular, it will summarize the findings of SK hynix’s breakthrough study on 20 nanometer (nm) SSM which were first revealed at International Electron Devices Meeting (IEDM) 2022.

¹Compute Express Link (CXL): PCIe-based next-generation interconnect protocol on which high-performance computing systems are based.

SK hynix’s SSM: Overcoming the Limitations of 3DXP

The phase-change memory (PCM)² product 3D XPoint (3DXP)³ gained significant attention for its high capacity, low latency, and byte-addressability. However, 3DXP has various shortcomings which hinder its application for CXL. For example, although 3DXP provides high capacity due to its small cell feature size (F) of 4F² and application of 2z⁴ nm process technology, further scaling is expected to face limitations. This is because PCM is susceptible to thermal disturbance (TDB)⁵ due to the smaller spaces between the cells, restricting its scaling potential. In terms of integration, since the 3DXP cell stack consists of a thick PCM, an ovonic threshold switch (OTS)⁶, and multiple electrodes, it has a very high aspect ratio (AR)⁷. In addition, PCM and OTS consist of “floppy” chalcogenides of which 20-30% are void or defect, which can lead to a leaning or wiggling phenomenon.

²Phase-change memory (PCM): A technology which enables nonvolatile electrical data storage at the nanometer scale. A PCM device consists of a small active volume of phase-change material placed between two electrodes. A common PCM material is germanium-antimony-tellurium (GeSbTe).

³3D XPoint (3DXP): A non-volatile phase change technology that serves as both memory and storage.

⁴2z: The third generation of 20 nm process technology in which “z” refers to the lower third number range of the 20 nm class, which covers 20 nm-29 nm. The letters “x”, “y” and “z” are used to refer to the upper, middle, and lower thirds, respectively, of the relevant process technology class such as 10 nm, 20 nm etc.

⁵Thermal disturbance (TDB): Inadvertently altering the state of a cell by programming another cell in its vicinity.

⁶Ovonic threshold switch (OTS): A two-terminal symmetrical voltage sensitive switching device which, after being brought from the highly resistive state to the conducting state, returns to the highly resistive state when the current falls below a holding current value.

⁷Aspect ratio (AR): The ratio of height to width. A high aspect ratio means that the structure is narrow but tall.

With the limitations of 3DXP clear to see, SK hynix shared the excellent array operation performance of its 20 nm SSM for the first time at IEDM 2022. SSM has a single cell stack, consisting of a cell material (dual function material), two electrodes, and two metal wires, which acts as both memory and selector in bi-directional operations. This simple stack enables SSM to overcome the scaling limitations of conventional PCM.

Figure 1. Cross section transmission electron microscopy (TEM) of an SSM cell stack (left) and the plan-view scanning electron microscopy (SEM) of eight mats making up a 32 Mb array (right)

 

It is widely known that chalcogenide-based devices such as 3DXP have a large Vt distribution. Figure 2 shows that SSM successfully obtained a suitable read window margin (RWM)⁸, the main hurdle for high density array operation, using cell stack materials engineered with the help of bipolar write operations. Sufficient RWM can be obtained even below a write pulse of 20 nanoseconds (ns) for both set and reset states, and at a much lower write current than conventional 3DXP. This guarantees extremely low write latency and power consumption. Moreover, the low write current and short write pulse means that SSM is placed under significantly less operational stress than 3DXP. Therefore, SSM offers superior write cycle endurance of up to 10 million (1E7) cycles.

⁸Read window margin (RWM): The threshold voltage (Vt) interval (ΔVt) at distribution tails. When using a chalcogenide material such as PCM, it has a Vt distribution similar to DRAM or NAND. The Vt interval between the Vt distribution of 0 and 1 is regarded as the sensing margin, or the read window margin.

Figure 2. Innovative cell stack engineering and material development enabled SSM to achieve a larger RWM than 3DXP

 

Determining the Composition Distribution of SSM

The fundamental operational mechanism of SSM is thought to be related to the atomic migration model. The vertical composition distribution of dual function material (DFM) cells in SSM can be detected by energy dispersive spectroscopy (EDS)⁹. As seen in Figure 3, clear differences are detected in the top, middle, and bottom layers when the set and reset bias are applied in opposite directions. In this case, an increase in atomic migrations is detected when the atoms have more electronegativity¹⁰. However, the atomic migration model combined with conventional transport theory fails to explain the voltage difference. Further research is therefore needed to come up with a theoretical explanation for this phenomenon.

⁹Energy dispersive spectroscopy (EDS): A chemical microanalysis technique which detects X-rays emitted from the sample during bombardment by an electron beam to identify the elemental composition of the sample.

¹⁰Electronegativity: The ability of an atom to attract shared electrons when forming a chemical bond.

Figure 3. The vertical composition distribution of DFM cells in SSM detected by EDS

 

Due to the elimination of phase change material, SSM showed no write disturbance (thermal disturbance) which can help improve the total system power consumption and performance. In addition, scaling is expected to have a smaller effect on SSM cell characteristics than found in 3DXP. When the cell critical dimension (CD), which refers to the cell width or length, is reduced from 18 nm to 15 nm in the same pitch, the change of voltage is relatively minimal. In light of this, SSM is expected to have more scalability than 3DXP.

Figure 4. Specification comparison of 3DXP and SSM (Source: T.Kim et al, IEDM2018)

 

Application With CXL & VSOM in the Future

SK hynix has demonstrated the successful array operation of 20 nm SSM for high-density memory applications as a successor to 3DXP. SSM outperforms 3DXP in terms of write latency, cell power consumption, and reliability. Moreover, the lower aspect ratio seems promising for the scaling of nodes below 1z nm. When coupled with its excellent latency and low power consumption, SSM is well-placed to make up for the deficiencies of 3DXP and be applied to CXL memory and vertical SOM in the future.

 

For more information regarding RTC’s research, please visit the center’s research website (https://research.skhynix.com). The RTC operates the site to share insights on its ongoing research of future technologies and to actively communicate with various global research organizations.