Press Release

HEI Develops Self-Designed NON-Memory Chio Manufacturing Process with a Circuit Width of 0.25μ

By December 12, 1998 December 9th, 2019 No Comments
– Plans to produce ASICs(application specific integrated circuit) and SOCs M(system-on-chip) from ’99
– Utilizes the existing 4M DRam product facility to manufacture high value Madded non-memory chips

HEI(president : Kim Young-Hwan) has developed self-designed non-memory logic technology with a circuit width of 0.25 micron that can be applied to mass producing readily.

The newly developed 0.25μ logic technology is a state-of-the-art technology that can be used in manufacturing products with high-speed and low electric consumption needs that are required in future telecommunication and multimedia fields and also high value added SOCs(System-on-Chip) chips that integrate non-memory and memory chips in one semiconductor chip.

The new technology has been developed by only a few leading chip makers abroad at present, and is considered to be on the same level or higher compared to making 1 giga DRAM manufacturing process technology.

The worldwide market for ASIC products only, applying the logic technology is estimated to reach about USD12 billions by 2000, and HEI plans to apply the technology from ’99 in the fields like system IC products, state-of-the-art ASICs and foundry business. Compared to non-memory chip manufacturing technology that are widely used at present with a circuit width of 0.35μ, by enhancing integration density by two times(decreasing the size of the chip by half) and cutting power consumption by 70%, HEI’s newly developed technology will be able to compete in international market with confidence. In particular, as HEI has succeeded in developing technology of utilizing low grade memory product line in producing high value added non-memory products by replacing 4MDRAM product line equipment only in some part, it was able to maximize product line efficiency.

HEI’s 0.25μ non-memory manufacturing technology adopts unit manufacturing process with electricity effective channel length under 0.18 μ, gate-oxide of 5nm thick, running voltages of 2.5V/3.3V and 5 layer metal wiring design technology with minimum circuit width of 0.25μ.

In addition, test chips using this technology, by securing gate delay time of 45psec and a certain number of products that can be produced, have made progress by being able to apply the technology in manufacturing products right away. HEI has advanced into the next phase in it’s self developing capacity of non-memory chip manufacturing process technology by succeeding in self-developing 0.25μ non-memory chip manufacturing process only after 9 months since it has succeeded in jointly developing 0.35μ logic technology with it’s once subsidiary in U.S. but sold, Symbios. In result, HEI will be able to strengthen it’s product competitiveness in high value added non-memory chip market which is under shifting phase from the size of 0.35μ to 0.25μ. In result, including integrated MML(merged memory logic) producing technology with a circuit width of 0.21μ which was developed in last September, HEI has acquired all the state-of-the-art manufacturing technologies that are crucial in system IC field, and with these technologies in hand, it is expecting to strengthen its non-memory chip field further.