Memory performance growth is quickly reaching an inflection point. Although memory providers suggest that certain levels of power, thermal, and area costs are inevitable to secure the required effective bandwidth performance, proponents of the system-on-chip (SoC) industry counter that the level of trade-offs should be maintained at the minimum considering fixed system-level budgets. These conflicting views highlight the need for the industry to build clear roadmaps and define new memory architecture and standards.
As an industry leader, SK hynix works to propel the HBM3 market forward by initiating industry collaboration and partnerships and innovating solutions like its HBM2E and HBM3 products, released in 2019 and 2021, respectively.
Sungsoo Ryu, Head of SK hynix DRAM Product Planning, and Sunghak Lee, Technical Leader of SK hynix In-Package Memory (IPM) Product Planning, introduced how their teams are maintaining the company’s long-term strategy in their second EE Times column. The duo’s previous column explored how HBM3 is helping to meet higher demands on DRAM and memory.
Ryu’s DRAM Product Planning team aims to deliver a new HBM line-up once every two years whilst continuing internal and external efforts to increase HBM products’ speed, density, power, and area.
As the industry continues deliberating on optimal performance targets, reaching a consensus will be a crucial step toward activating SK hynix’s HBM roadmap. Meanwhile, the DRAM Product Planning team will continue working with partners to tackle existing technical issues and maintain its industry leadership position.
Read the full article on EE Times: SK hynix DRAM Product Planning Spearheads the Memory Evolution in the Post-HBM3 Era
